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Design >> Analog Design >> Design of CMOS PLL with Ring VCO
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Message started by Bomestantin on Aug 29^th, 2016, 10:00pm

Title: Design of CMOS PLL with Ring VCO
Post by Bomestantin on Aug 29^th, 2016, 10:00pm

I need to design PLL that works in wide frequency range and have a small power consumption. So i desided to use Ring VCO in this PLL. Also i am using TSPC frequency divider, because PLL should have pretty high max frequency. The problem is, that Ring VCO has a wider working frequency range than divider. If in locking process voltage on tune input of VCO will be too small or high - PLL fails to lock. I am working on pretty lame process so due to PVT i have to do VCO with wide frequency range, and also due to PVT i can't do wider range of divider. What can i do with this?

Title: Re: Design of CMOS PLL with Ring VCO
Post by vroy_92 on Sep 2^nd, 2016, 8:54am

Split the locking process into two parts:
During the first part, do not close the PLL loop through the feedback divider but do some sort of calibration to bring the frequency close enough to whatever frequency you want the PLL to lock at.
And then the close the loop so that the phase will be locked.

Alternatively, you can put a divide by 2 at the front of the feedback divider but then you would be limited solely to even division ratios.

I strongly recommend doing a frequency calibration first.