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Design Languages >> Verilog-AMS >> Do not use the `absdelay' analog operator in a conditionally-executed statement
https://designers-guide.org/forum/YaBB.pl?num=1472538740

Message started by Rosh on Aug 29^th, 2016, 11:32pm

Title: Do not use the `absdelay' analog operator in a conditionally-executed statement
Post by Rosh on Aug 29^th, 2016, 11:32pm

Hello,

I am trying to simulate the following code

Code:

@(cross( V(utility)- V(ref),1))

begin
V(tout)<+ absdelay(V(dut),10n);

end

However, the error states I cannot embed an "absdealy" statement in a conditional executed statement.

Is there any workaround for this?

Thank you,
Rosh

Title: Re: Do not use the `absdelay' analog operator in a conditionally-executed statement
Post by Geoffrey_Coram on Aug 30^th, 2016, 11:08am

What are you trying to do??

What do you think happens on the "tout" terminal (port) when the cross event is not active?

What you've written, if any simulator were to try to implement it, would say that you want V(tout), at the instant that V(utility) - V(ref) crosses 0, to be a delayed sample of V(dut) from 10n earlier, and otherwise there is no contribution to the "tout" port. That doesn't make any sense.

Title: Re: Do not use the `absdelay' analog operator in a conditionally-executed statement
Post by Rosh on Aug 31^st, 2016, 8:12pm

What exactly doesn't make sense here?

If utility crosses a reference voltage, V(tout) should be a delayed version of V(dut)?
How would I write such a statement then?

Geoffrey_Coram wrote on Aug 30^th, 2016, 11:08am:

Title: Re: Do not use the `absdelay' analog operator in a conditionally-executed statement
Post by Geoffrey_Coram on Sep 2^nd, 2016, 11:29am

What happens if utility doesn't cross the reference voltage?

Your cross statement only says what the model should do at the exact moment of crossing; you haven't said what happens for all the other timepoints of the simulation.

Title: Re: Do not use the `absdelay' analog operator in a conditionally-executed statement
Post by Geoffrey_Coram on Sep 2^nd, 2016, 11:38am

I would think you want something more like this:

Code:

real vout, vsamp;
@(initial_step) begin
vout = 0;
end

vsamp = absdelay(V(dut),10n);
@(cross( V(utility)- V(ref),1)) begin
vout = vsamp;
end

V(tout)<+ vout;

At the crossing, this captures a sample from 10n earlier, and holds this until the next crossing. But I don't know if you wanted a hold, or if you wanted the output to be zero between crossings, or if you wanted the output to be zero until a crossing, and after the crossing to track (a delayed copy of) the input.