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Design Languages >> Verilog-AMS >> Rules and conditions enforced on signal-flow systems
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Message started by JayOcad on Sep 8^th, 2016, 12:51pm

Title: Rules and conditions enforced on signal-flow systems
Post by JayOcad on Sep 8^th, 2016, 12:51pm

What rules or conditions are enforced on signal-flow systems if any?

I read that potential signal-flow systems don't enforce KFL, is KPL enforced or are there just absolutely zero conditions imposed on signal-flow systems and flow and potential have no difference?

I searched around for days and went through the Verilog-ams books but for the life of me can't find the list of conditions that the solver/compiler enforces when only one nature is specified for signal-flow systems.

Many thanks.

Title: Re: Rules and conditions enforced on signal-flow systems
Post by Ken Kundert on Sep 8^th, 2016, 11:48pm

No rules, no conditions. The only difference is you cannot access the missing nature.

-Ken