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Design >> Mixed-Signal Design >> A Question about incremental ADC
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Message started by watt.xu on Sep 9^th, 2016, 1:31pm

Title: A Question about incremental ADC
Post by watt.xu on Sep 9^th, 2016, 1:31pm

Hello everyone:
I found there is not a lot concrete materials on reset timing on the Incremental ADC. Right now I am doing a MASH 2+2 structure incremental ADC. assume there will be a ideal digital error cancellation logic (digital differentiator ) on 2nd stage path as (1-z^-1)^2. May I ask how large the delay is introduced in this differentiator? Intuitively I thought it is two regardless reset cycles? Please let me know your ideas.
since in incremental adc application, we will reset every OSR cycles, these block introduce large delay is not good.

Title: Re: A Question about incremental ADC
Post by deba on Oct 15^th, 2016, 12:09am

Could you post your block diagram?

The delay should be such that the quantization noise is cancelled from the first stage.