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Simulators >> Circuit Simulators >> Disable updating DefValue of CDF Parameter from Verilog-A in Cadence IC6
https://designers-guide.org/forum/YaBB.pl?num=1473953010

Message started by cheap_salary on Sep 15^th, 2016, 8:23am

Title: Disable updating DefValue of CDF Parameter from Verilog-A in Cadence IC6
Post by cheap_salary on Sep 15^th, 2016, 8:23am

DefValue of CDF parameters are updated from "parameter statement" in Verilog-A everytime I save Verilog-A code in Cadence IC6.

However this operation is troublesome.
DefValue of CDF parameters were not affected at all in Cadence IC5.

Is there any method to disable this operation in Cadence IC6 ?

Code:

parameter real Tari = 6.25u from [6.25u:25u];
parameter real Delimiter = 12.5u from [0.95*12.5u:1.05*12.5u];
parameter real Tsymb_0 = Tari;
parameter real Tsymb_1 = 2*Tari from [1.5*Tari:2*Tari];
parameter real RTcal = 2.75*Tari from [2.5*Tari:3*Tari];
parameter real TRcal = 2*RTcal from [1.1*RTcal:3*RTcal];
parameter real Tpw = 0.5*Tari;
parameter real tt = 0.33*Tari from (0.0:0.33*Tari]; //transition time of output