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Simulators >> Circuit Simulators >> Generating and using components in for-loops in spice
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Message started by kiltanen on Sep 22^nd, 2016, 10:55am

Title: Generating and using components in for-loops in spice
Post by kiltanen on Sep 22^nd, 2016, 10:55am

I have a model that has MxN components connected to each other with another component in lateral and horizontal directions, which I want to simulate with Spice. As M and N get many different values the components and their connections have to be generated with a for-loop or equivalent solution. How can system to be realized in Spice, can components and nodes placed into vector or is somekind systematical naming scheme required? A diagram of network attached.

Title: Re: Generating and using components in for-loops in spice
Post by Geoffrey_Coram on Sep 23^rd, 2016, 7:37am

I've seen schematic interfaces that allow "iterated components" where you can use vector notation for them (and the nodes connected to their terminals). But I think these are expanded into a "systematical naming scheme" that you mention.

You might be able to do something with the generate statement in Verilog-AMS, if your simulator supports that.

Otherwise, I think you'll have to write a script that generates your netlist, and then you might as well come up with a naming scheme, in case your Spice simulator doesn't like vectors.