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Design Languages >> Verilog-AMS >> Modeling jitter using simple VCO in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1474626903

Message started by ksnf3000 on Sep 23^rd, 2016, 3:35am

Title: Modeling jitter using simple VCO in Verilog-A
Post by ksnf3000 on Sep 23^rd, 2016, 3:35am

Hi,

I am trying to model jitter in verilog-A using a simple vco. Please see the below code for it. I hvae written the testbench but its not good. Could you please point me where the mistake is in the testbench? Once I have compiled this, how do I run this in eldo? Thanks!

VCO module:

Code:

`include "constants.vams"
`include "disciplines.vams"

module jitter_analysis_vco(out,in);

input in;output out;electrical out,in;

parameter real Vmin=0;
parameter real Vmax=Vmin+1 from (Vmin:inf);
parameter real Fmin=1 from (0:inf);
parameter real Fmax=2*Fmin from (Fmin:inf);
parameter real ratio=1 from [1:inf);
parameter real Vlo=0,Vhi=1;
parameter real tt=0.01*ratio/Fmax from (0:inf);
parameter real jitter =0 from [0:0.25/Fmax);
parameter real ttol = 1e-6/Fmax from (0:1*ratio/Fmax);

real freq,phase,dT;
integer n,seed;

analog begin
@(initial_step) begin
seed=-718;
end

freq = (V(in)-Vmin)*(Fmax-Fmin)/(Vmax-Vmin)+Fmin;

if(freq>Fmax) freq=Fmax;
if(freq<Fmin) freq=Fmin;

//add the phase noise
freq=freq/ratio;
freq=freq/(1+dT*freq);

//phase is the integral of the freq modulo 2 pi
phase=2*`M_PI*idtmod(freq,0.0,1,-0.5);

//update jitter twice per second
@(cross(phase+`M_PI/2,+1,ttol) or
cross(phase-`M_PI/2,+1,ttol)) begin
dT = sqrt(2*ratio)*jitter*$dist_normal(seed,0,1);
n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
end

//generate the output
V(out) <+ transition(n ? Vhi:Vlo,0,tt);
end

endmodule

Testbench code:

Code:

`timescale 10ns / 10ps
//`timescale 100ps / 10fs
`include "disciplines.vams"

connectrules myRules;
connect jitter_analysis_vco input electrical, output electrical;
endconnectrules

connectmodule jitter_analysis_vco (out, in);

initial begin
case(in)
1'b0: begin v = 0;end
1'b1: begin v = 1;end
1'bx: begin v = 0.5; end
1'bz: begin v = 0.5; end
endcase
end

always @in begin
case(in)
1'b0: begin v = 0; end
1'b1: begin v = 1; end
1'bx: begin v = 0.5; end
1'bz: begin v = 1;end
endcase
end

analog
V(out) <+ transition(v, 0, 10p, 10p) + transition(r, 0, 10p, 10p)*I(out);
endmodule

Thanks a lot for your help!

Title: Re: Modeling jitter using simple VCO in Verilog-A
Post by Geoffrey_Coram on Sep 23^rd, 2016, 7:32am

How is "r" set?

V(out) <+ transition(v, 0, 10p, 10p) + transition(r, 0, 10p, 10p)*I(out);

Title: Re: Modeling jitter using simple VCO in Verilog-A
Post by ksnf3000 on Sep 26^th, 2016, 4:38am

Please ignore the r. Please let me know how to continue with the testbench writing.