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Design >> RF Design >> accumulated jitter vs phase noise in PLL
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Message started by dog1 on Sep 27^th, 2016, 5:00am

Title: accumulated jitter vs phase noise in PLL
Post by dog1 on Sep 27^th, 2016, 5:00am

Hello,

I am reading the paper from Kim and Pual Gray PLL/DLL system noise analysis for low jitter clock synthesizer design. Here I encounter the concept accumulated jitter for the first time. It says that by accumulating jitter in different cycles of PLL, it can be amplified, compared with the jitter from the VCO. This is bugs me. Because using the normal s domain analysis of PLL, we know that the phase noise of the PLL is high pass filtered. This means that the energy of phase noise/ rms jitter should be smaller compared with that of VCO. However, this paper indicates otherwise. Can anyone comment on that?

Additionally, does anyone know if the accumulated noise is taken into account of in jitter simulation using spectre?

Thanks

CHEN

Title: Re: accumulated jitter vs phase noise in PLL
Post by Ken Kundert on Sep 28^th, 2016, 11:24pm

Accumulating jitter is just another name for the phase noise of the oscillator. The fact that the phase noise goes to infinity as the offset frequency goes to zero is equivalent to saying that the jitter accumulates from cycle to cycle and causes the phase to drift without bound.

But the jitter only accumulates when it is running open loop. When the loop is closed it acts to suppress the close-in noise, and equivalently, locks in the phase so it cannot drift, meaning that the accumulation of the jitter is also suppressed.

Yes, Spectre accounts for accumulating jitter.

-Ken

Title: Re: accumulated jitter vs phase noise in PLL
Post by dog1 on Sep 30^th, 2016, 2:35am

Hello Ken,

Thanks very much for your reply. It is good to know that accumulated jitter is just another name of jitter and phase noise. I will check again the IEEE paper and see if the calculation there correspond to normal PLL. Thanks:)

BR

CHEN