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Simulators >> AMS Simulators >> ams simulator timing problem
https://designers-guide.org/forum/YaBB.pl?num=1475779911

Message started by liletian on Oct 6^th, 2016, 11:51am

Title: ams simulator timing problem
Post by liletian on Oct 6^th, 2016, 11:51am

Hi All

I am trying to speed up the ams simulator by using behavior model. However, the behavior model does not generate correct results. It seems to due to the timing problem. It used to have some .libs for ams simulator, but right now I only have fixed rising, falling time and delay in the behavior model. Can anyone comments on how to solve this problem?

The timing violation looks like this

Warning! Timing violation
$setuphold<setup>( posedge CK &&& (flag == 1):209850883146 FS, negedge D:209850830504 FS, 1.000 : 1 NS, 0.500 : 500 PS );
File:DFFRHQX1/functional/verilog.v, line = 44
\instClash_reg_address_reg[4]
Time: 209850883146 FS

tran: time = 210 us (55.3 %), step = 72.47 ps (19.1 u%)
tran: time = 210.1 us (55.3 %), step = 83.37 ps (21.9 u%)
tran: time = 210.2 us (55.3 %), step = 16.21 ps (4.27 u%)
tran: time = 210.6 us (55.4 %), step = 83.96 ps (22.1 u%)
tran: time = 210.7 us (55.5 %), step = 154.7 ps (40.7 u%)
tran: time = 210.9 us (55.5 %), step = 10.79 ps (2.84 u%)
tran: time = 211 us (55.5 %), step = 77.62 ps (20.4 u%)

Warning! Timing violation
$setuphold<setup>( posedge CK &&& (flag == 1):211043873290 FS, negedge D:211043830474 FS, 1.000 : 1 NS, 0.500 : 500 PS );
File:
/DFFRHQX1/functional/verilog.v, line = 44
Scope: instClash_reg_address_reg[4]
Time: 211043873290 FS

tran: time = 211.1 us (55.6 %), step = 137.8 ps (36.3 u%)
tran: time = 211.3 us (55.6 %), step = 73.09 ps (19.2 u%)
tran: time = 211.4 us (55.6 %), step = 136 ps (35.8 u%)
tran: time = 211.8 us (55.7 %), step = 160.5 ps (42.2 u%)
tran: time = 211.9 us (55.8 %), step = 63.67 ps (16.8 u%)
tran: time = 212 us (55.8 %), step = 30.07 ps (7.91 u%)
tran: time = 212.2 us (55.8 %), step = 541.7 ps (143 u%)

Warning! Timing violation
$setuphold<setup>( posedge CK &&& (flag == 1):212236883152 FS, negedge D:212236830468 FS, 1.000 : 1 NS, 0.500 : 500 PS );
File: /DFFRHQX1/functional/verilog.v, line = 44
Scope: instClash_reg_address_reg[4]
Time: 212236883152 FS

Thanks,

Title: Re: ams simulator timing problem
Post by AMS_ei on Apr 19^th, 2017, 9:16am

Hi,

One thing I can suggest is that delay must be annotated to 100%.
Could you please check the annotation statistics if it is 100%?

Hope this helps.

Thank you.

Kind regards