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Design Languages >> Verilog-AMS >> Long simulation time with two VCO verilog A modules
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Message started by saralandry on Nov 14^th, 2016, 3:23am

Title: Long simulation time with two VCO verilog A modules
Post by saralandry on Nov 14^th, 2016, 3:23am

Hi,

I am simulating a VCO-based ADC with Spectre. Verilog-A module is used for the VCO. D flip-flop and Xor gate are all from ahdlLib.
My sampling frequency is 640 MHz and the VCO free running frequency is fs/2. My simulation time is also 6.8 us to get 4096 points for FFT.
Let's say I am simulating the standalone one (just one VCO-based ADC in the schematic). The simulation time is about 7 minutes in the liberal mode. When I add another VCO-based ADC in the schematic (two VCO-based ADC in the schematic) the simulation time goes up to about 50 minutes in the liberal mode. It is kind of weird to me.

Can anyone kindly explain why this happens and let me know how to deal with? I mean reducing the simulation time when I am using VCOs.

My gut tells me that there is supposed to be a solution for this problem.

Thank you

Title: Re: Long simulation time with two VCO verilog A modules
Post by deba on Nov 14^th, 2016, 5:28am

When you say two VCO based ADCs, I assume that they are somehow connected.

The simulation time is directly proportional to the smallest time difference present in the circuit. I guess the two VCOs are oscillating close to each other, and there edges might be nearby, resulting in a smaller time step.
Thus, a longer simulation time.

Title: Re: Long simulation time with two VCO verilog A modules
Post by saralandry on Nov 14^th, 2016, 8:59am

Hi deba,

Yes, you're right. Both VCOs are oscillating with the same free-running frequency.
So, Is there any way to speed up the simulation?

Thank you,

Title: Re: Long simulation time with two VCO verilog A modules
Post by deba on Nov 19^th, 2016, 7:40pm

Hi

As far as I know, there is no way to reduce the minimum time step. You can force a time step in the simulator but at the cost of accuracy.

Thanks