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Simulators >> Circuit Simulators >> How to enforce a syntax error when using an undeclared variable in HSPICE?
https://designers-guide.org/forum/YaBB.pl?num=1479927062

Message started by AA on Nov 23^rd, 2016, 10:51am

Title: How to enforce a syntax error when using an undeclared variable in HSPICE?
Post by AA on Nov 23^rd, 2016, 10:51am

When using a Verilog-A module in HSPICE, if you misspell a variable name, the module will compile and replace the misspelled variable with a 0.

How can I make HSPICE throws an error and stop compilation when a misspelling of a variable name occurs (assuming the misspelled variable is not declared)?

To reproduce the issue/point I'm talking about, here is an HSPICE netlist:

Code:

* simple voltage divider
.hdl 'cut.va'

V n1 0 dc 10
R1 n1 n2 1k
xR2 n2 0 va_resistor resv=1k

.tran 0.1n 1.1n

.meas tran vn2 find V(n2) at=1n

.option brief nomod accurate abstol=1e-9 reltol=1e-9 ingold=2
.option measform=3
.option SEED=541

.end

And the "cut.va" resistor module:

Code:

`include "disciplines.vams"
`include "constants.vams"

module va_resistor(n,p);
inout n,p;
electrical n,p;

parameter real resv=3k;

// this real variable is just to show my point
real resistor_value;

analog begin
@(initial_step) begin
// no spelling mistake here
resistor_value = resv;
end

// note the spelling error "resister_value" instead of "resistor_value"
V(n,p) <+ resister_value * I(n,p);
// and yet, HSPICE allows this, and replaces the undeclared variable with a valie of zero!
end

endmodule

Note that HSPICE does not produce an error and just auto-declares a new variable with the same type initialized to 0:

Code:

*pvaW* variable 'resister_value' is used without declaration, set to real (cut.va:20)

How to prevent the "auto-declare" functionality and mandate all variables to be explicitly declared? I hope there is an option for this.