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Design >> Analog Design >> layout for large capacitors
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Message started by rames on Nov 30^th, 2016, 7:46am

Title: layout for large capacitors
Post by rames on Nov 30^th, 2016, 7:46am

I use tsmc18rf in 180nm technology in Cadence for make layout for my circuit. I have large capacitors in order of 10pF. I used "MIMCAP" for implementation of these large capacitors.
but they occupy large spaces in my layout. I want to use other kinds of capacitors if possible. I wanted to use poly1-poly2 capacitors to small the layout but i have no contact for poly2 to metal.
Do you know how to implement large capacitors in cadenece? is there any way to implement poly1-poly2 capacitors in cadence?
Thanks in advance

Title: Re: layout for large capacitors
Post by loose-electron on Dec 8^th, 2016, 10:04pm

MIMCAP structures do not have a lot of capacitance per unit area due to the thick oxide layers between metal layers. (True of many foundry processes, but all are unique)

If you can use a ground or power rail tied capacitor, that is nonlinear consider using the gate of NMOS or PMOS device.

Title: Re: layout for large capacitors
Post by tzg6sa on Dec 9^th, 2016, 1:50am

I would first check whether poly1-poly2 is available. Using them increase the cost of every wafer and therefore often this option is not used.

About the connection: look at the documentation of the technology. There must be anything related to it. The last chance would be to look how to connect poly2 to M1. I can image that it requires the same via as poly1.

Title: Re: layout for large capacitors
Post by tenso on Dec 14^th, 2016, 11:40pm

is poly-poly more expensive than MIM even if the latter has a lower capacitance per unit area and thus covers more area?