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Simulators >> AMS Simulators >> DC Simulation using verilog AMS in config view
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Message started by Lavanya on Dec 1st, 2016, 2:00am

Title: DC Simulation using verilog AMS in config view
Post by Lavanya on Dec 1st, 2016, 2:00am

I am using cadence virtuoso version 6.1.6-64b.500.4, in that verilog AMS view is used. After code is entered in the AMS code window, symbol has been created, for simulation schematic test bench and config view for the same test bench has been created . Generally, in verilog AMS module in the port list we will give input and output terminals and if we want transient analysis, from ADE window, we choose analysis->trans->stop time->enable->outputs to be plotted->select on design->we will select input and output pins, then a graph window pops up. Here input and output pins are the terminals that we give in port list in the code. Now the problem is, suppose if i want a plot for the expression which is used in the code where for that expression the terminals are not defined in the port list to select while outputs to be plotted. what is the solution for this, and how can i plot the graph. For example, port list is module xxx(T1,T2,x) and the expression used in the code is R=V/I; How to plot the graph between R and V.(R on y-axis and V on x-axis)

Title: Re: DC Simulation using verilog AMS in config view
Post by AMS_ei on Mar 19th, 2017, 9:42am

Hi Lavanya,

You could easily achieve it by creating a probe.tcl file. Typical example of such file is shown below:
----------example of probe.tcl file---------------
database -open waves -into waves.shm -default
probe -create testbench -depth all -shm -waveform
run
exit
---------end of probe.tcl file----------------------

You can give it to irun with the following option: -input probe.tcl

This will create a waveform database called waves.shm and you can open this database with simvision by typing the following command:

simvision waves.shm &

Hope this helps.

Thank you.


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