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Design Languages >> Verilog-AMS >> Access bits of integer
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Message started by Gornarok on Dec 11^th, 2016, 9:44am

Title: Access bits of integer
Post by Gornarok on Dec 11^th, 2016, 9:44am

Hello,
Id like to make a modul that has integer as input and outputs its value as bits. Is it possible to access bits of integer? Or can I converse integer to bit vector? What would the best way to do it?

I wanted to do something like this:

Code:

analog begin

generate i (fN-1,0)begin
V(filter_out[i]) <+ filter_in[i] ? V(vdd): V(vssr);
end

generate i (gN-1,0) begin
V(gain_out[i]) <+ gain_in[i] ? V(vdd): V(vssr);
end
end

Title: Re: Access bits of integer
Post by Ken Kundert on Dec 13^th, 2016, 5:38pm

The easiest way to do this is to do a bit-wise and. So something like:

Code:

generate i (gN-1,0)
V(gain_out[i]) <+ transition(gain_in & (1 << i) ? 1 : 0, 0, 1u) * (V(vdd) - V(vssr)) + V(vssr);

Use of the transition function is also important.

Use of genvars is now preferred over use of the generate statement, so you should probably use:

Code:

genvar i;
for (i = 0; i < gN; i = i+1)
V(gain_out[i]) <+ transition(gain_in & (1 << i) ? 1 : 0, 0, 1u) * (V(vdd) - V(vssr)) + V(vssr);

-Ken