The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> RF Design >> PLL predivision for harmonic reason
https://designers-guide.org/forum/YaBB.pl?num=1484321008

Message started by dog1 on Jan 13^th, 2017, 7:23am

Title: PLL predivision for harmonic reason
Post by dog1 on Jan 13^th, 2017, 7:23am

Hello everyone,

I remembered that it is beneficial to have the PLL reference clk pre-divided before feeding into the PLL to reduce the effect of harmonics, but I cannot remember how it is reasoned, nor can I reason it myself. Can anyone help me with that?

Thanks:)

CHEN

Title: Re: PLL predivision for harmonic reason
Post by subtr on Jan 31^st, 2017, 10:41pm

If you pre divide the reference clock, then it's not going to be good in terms of reference spur. The PLL bandwidth was already kept lower than undivided reference clock. Now if you lower your frequency of reference, then more harmonics of your reference feedthrough will come inside the PLL band. This is bad because now VCO is going to react to these spurs resulting in more jitter. Now what is advantage of dividing the clock? Your phase detector range increases. The same time difference between your reference and feedback clock now represents a smaller phase which means phase detector range has improved. But this comes at the cost of reduced gain.