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Measurements >> Phase Noise and Jitter Measurements >> how to build pll noise model based on verilog-a using Ken Kundert‘s method?
https://designers-guide.org/forum/YaBB.pl?num=1484707347

Message started by lwzunique on Jan 17^th, 2017, 6:42pm

Title: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 17^th, 2017, 6:42pm

Hi,everyone.

I am beginner of PLL circuit design, recently I want to do analysis about the phase noise of PLL. and I found Ken Kundert's Paper:Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.
there are several problems that confuse me so much.
1.if I want to copy your code about other listings, I have to put phase.vams into the directory the same as disciplines.vams, correct?
2.I can't compile the code for divider, the detail is shown bellow.

3.suppose that I have build all the blocks correctly, what should I do to have the overall phase noise, how to connect these blocks in the schematic in candence platform, and what simulation should I do，AC or Noise？

4.if I have get the phase noise data of all the blocks made by real process like TSMC or globafoundry. how
to build the verilog-a model to combine this noise data together to get the pll out's overall phase noise.

thanks everybody!

William

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 17^th, 2017, 10:54pm

lwzunique wrote on Jan 17^th, 2017, 6:42pm:

1.if I want to copy your code about other listings, I have to put phase.vams into the directory the same as disciplines.vams, correct?

Correct, if you don't want to specify absolute path for "phase.vams".

However I recommend you to specify absolute path for "phase.vams" and place it in any directory.

lwzunique wrote on Jan 17^th, 2017, 6:42pm:

2.I can't compile the code for divider, the detail is shown bellow.

What error do you get ?
Show us details.

lwzunique wrote on Jan 17^th, 2017, 6:42pm:

3.suppose that I have build all the blocks correctly, what should I do to have the overall phase noise,
how to connect these blocks in the schematic in candence platform,

See Listing.18.

lwzunique wrote on Jan 17^th, 2017, 6:42pm:

and what simulation should I do,AC or Noise?

Do Noise Analysis.

lwzunique wrote on Jan 17^th, 2017, 6:42pm:

4.if I have get the phase noise data of all the blocks made by real process like TSMC or globafoundry.
how to build the verilog-a model to combine this noise data together to get the pll out's overall phase noise.

Adjust "n", "fc", "jitter", etc.

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1275390599
http://www.designers-guide.org/Forum/YaBB.pl?num=1444923186
http://een.iust.ac.ir/profs/Abrishamifar/Analog%20Integrated%20Circuit%20Design/Hspice/Other%20Helps/Predicting%20PLL%20Phase%20Noise%20&%20Jitter%20with%20HspiceRF.pdf
http://www.highfrequencyelectronics.com/index.php?option=com_content&view=article&id=1354:phase-locked-loop-noise-transfer-functions&catid=134:2016-01-january-articles&Itemid=189

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by Ken Kundert on Jan 18^th, 2017, 1:13am

The syntax accepted by Verilog-AMS has changed somewhat over the years. In particular, apparently the way that you give array literals has changed. So the noise table should probably be given as ...

Code:

Theta(out) <+ noise_table_log('{
1, n,
bw, n,
fmax, n*pow(fmax/bw), 2*order)
}, "dsn");

Notice the ' that initiates the array literal. Specifically, '{ ... }. Fixing that should probably clear up your syntax problem.

Also notice I switched to noise_table_log. That seems like that would probably be better than noise_table.

-Ken

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 2:06am

Quote:

Do Noise Analysis.

thanks @cheap_salary and Kundert, I have fixed the error in divider block, one part of the bracket was missing.
now i have built all the blocks, but the vco has no control terminal, as shown in the picture below, and I also don't know how to combine this blocks together？
[img][/img]

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 18^th, 2017, 2:17am

See Listing-1.
Your vco is not VCO.
Read documents surely.

VCO is Listing-4.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 2:28am

cheap_salary wrote on Jan 18^th, 2017, 2:17am:

See Listing-1.
Your vco is not VCO.
Read documents surely.

VCO is Listing-4.

Code:

`include “disciplines.vams”
module pll(out);
output out;
phase out;
parameter integer m = 1 from [1:inf); // input divide ratio
parameter real Kdet = 1 from (0:inf); // phase detector gain
parameter real Kvco = 1 from (0:inf); // VCO gain
parameter real c1 = 1n from (0:inf); // Loop filter C1
parameter real c2 = 200p from (0:inf); // Loop filter C2
parameter real r = 10K from (0:inf); // Loop filter R
parameter integer n = 1 from [1:inf); // feedback divide ratio
phase in, ref, fb;
electrical c;
oscillator OSC(in);
divider #(.ratio(m)) FDm(in, ref);
phaseDetector #(.gain(Kdet)) PD(ref, fb, c);
loopFilter #(.c1(c1), .c2(c2), .r(r)) LF(c);
vco #(.gain(Kvco)) VCO(c, out);
divider #(.ratio(n)) FDn(out, fb);
endmodule

In listing-1, how these definitions of the blocks know where I put the divider.va phaseDetector.va and so on?
I am not familiar with verilog-a either. thank you.
and when do simulation, I just simulate the single pll block in the schematic using noise analysis?

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 18^th, 2017, 2:45am

If you can not understand Verilog-A Language, can you understand Spectre or Spice Language ?

If you can understand either of Spectre or Spice Language, I can translate Lisiting-1 to them.

Verilog-A, Spectre and Spice are all circuit description languages.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 3:05am

cheap_salary wrote on Jan 18^th, 2017, 2:45am:

thanks@cheap_salary, I will study what your told me carefully and have a try. thank you.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 18^th, 2017, 4:21am

Ken Kundert wrote on Jan 18^th, 2017, 1:13am:

Notice the ' that initiates the array literal.
Specifically, '{ ... }.

At least, Cadence Spectre 14.1 don't show any warning even if without '.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by Ken Kundert on Jan 18^th, 2017, 4:00pm

The '{...} form is recommended in the latest Verilog-AMS LRM. It is something they picked up recently from SystemVerilog. This means that Verilog has two form for array literals, you can either use '{...} or {...}. The former represents packed arrays and the latter represents unpacked arrays. The '{...} form did not exist when Verilog-AMS first came out, so early versions of Verilog-AMS and Spectre only support the {...} form. I suspect that the more recent versions of Spectre are requiring the use of the '{...} form when specifying the array values to the laplace, zi, and table functions.

-Ken

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 7:46pm

I have built the schematic as shown below,but i don't know how to get the phase noise output.

I do the noise simulation, but the output curve is not as shown in the paper:Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 7:51pm

another problem is that, I want to simulate the noise of single VCO block, it can't work.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 18^th, 2017, 8:00pm

You don't reflect listing-1 at all.
Surely see listing-1.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 8:24pm

really sorry for my mistake.
now I think it is right.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 18^th, 2017, 8:36pm

Do you surely set nonzero value noise ?
If n is equal to zero, noise is not generated.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 18^th, 2017, 8:45pm

cheap_salary wrote on Jan 18^th, 2017, 8:36pm:

Do you surely set nonzero value noise ?
If n is equal to zero, noise is not generated.

I set the value of n, at now, i don't know how to set it correctly, I can get the equivalent output noise, the result is wrong. I will have further study about it.
thanks for your help, and really sorry for my carelessness, I am a newbie, sometimes something is really difficult for me. thanks again!

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 19^th, 2017, 4:34am

Ken Kundert wrote on Jan 18^th, 2017, 4:00pm:

The '{...} form is recommended in the latest Verilog-AMS LRM.
It is something they picked up recently from SystemVerilog.
This means that Verilog has two form for array literals,
you can either use '{...} or {...}.
The former represents packed arrays and the latter represents unpacked arrays.
The '{...} form did not exist when Verilog-AMS first came out,
so early versions of Verilog-AMS and Spectre only support the {...} form.

Thanks for explanations.

Ken Kundert wrote on Jan 18^th, 2017, 4:00pm:

I suspect that the more recent versions of Spectre are requiring the use of the '{...} form when specifying the array values to the laplace, zi, and table functions.

I confirmed both '{...} and {...} in Cadence Spectre 14.1.
There are no warning and error for both of them.
And results are same.

Cadence Spectre 14.1 accepts both '{...} and {...}.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 19^th, 2017, 4:36am

lwzunique wrote on Jan 18^th, 2017, 7:51pm:

another problem is that,
I want to simulate the noise of single VCO block,
it can't work.

Show me Spectre Netlist and Verilog-A code for VCO.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 19^th, 2017, 4:14pm

this figure is the phase noise of real vco.
and the code is:

Code:

// VerilogA for pllphasenoise, vco, veriloga

`include "constants.vams"
`include "/home/wzliu/project/phase.vams" // from Listing 2, includes disciplines.vams.

module vco(in, out);
input in; output out;
voltage in;
phase out;
parameter real gain = 40e6 from (0:inf); // transfer gain, Kvco (Hz/V)
parameter real n = 50 from [0:inf); // white output phase noise at 1 Hz (rad2/Hz)
parameter real fc = 500K from [0:inf); // flicker noise corner frequency (Hz)
analog begin
Theta(out) <+ 2*`M_PI*gain*idt(V(in));
Theta(out) <+ flicker_noise(n, 2, "wpn") + flicker_noise(n*fc, 3, "fpn");
end
endmodul

I can't understand rad2/Hz, what is the relationship between rad2/Hz and dBc/Hz?

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 19^th, 2017, 4:21pm

Show me Spectre Netlist of giving convergence error.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 19^th, 2017, 4:26pm

vco-test schematic and the simulation log output.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by cheap_salary on Jan 19^th, 2017, 4:30pm

Show me Spectre Netlist.

lwzunique wrote on Jan 19^th, 2017, 4:14pm:

I can't understand rad2/Hz, what is the relationship between rad2/Hz and dBc/Hz?

Surely see all equations in Ken's Document.

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 19^th, 2017, 4:33pm

cheap_salary wrote on Jan 19^th, 2017, 4:30pm:

Show me Spectre Netlist.

lwzunique wrote on Jan 19^th, 2017, 4:14pm:

I can't understand rad2/Hz, what is the relationship between rad2/Hz and dBc/Hz?

Surely see all equations in Ken's Dovument.

Code:

// Generated for: spectre
// Generated on: Jan 20 08:10:38 2017
// Design library name: pllphasenoise
// Design cell name: vco_test
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: pllphasenoise
// Cell name: vco_test
// View name: schematic
I0 (net3 net1) vco gain=4e+07 n=50 fc=500000
V0 (net3 0) vsource dc=1 type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
noise ( net1 0 ) noise start=1 stop=10M annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home/wzliu/project/fm394_wzliu.Work/pllphasenoise/vco/veriloga/veriloga.va"

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by Ken Kundert on Jan 19^th, 2017, 5:52pm

rad2/Hz means radians²/Hertz.

A VCO has no dc solution, so you should skip the dc analysis (specify 'skip dc' to the transient analysis).

-Ken

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 19^th, 2017, 6:33pm

in the paper: SΦ(Δf) is power density of phase, and L(Δf) is phase noise that we can get by doing pss and pnoise to a real vco, is this right?
and calculation of n and fc is based on the result of pss+pnoise.
how to use equation 21,26,29 to calculate n?
what does the fΔ in equation 25 mean? corner frequency, is it fc?
if i choose a Δf that is well above fΔ and well below fo, n=cfo^2*pi=L(Δf)*Δf^2*2,is this right?
in the figure below, at frequency 10^5Hz, the slope changes from -30dB to 20 dB, so fc is 10^5 Hz.
I choose Δf=100M to do the calculation. n= 2*10^(L(100M)/10)*2*(100M)^2=1.32.
then veriloga model of VCO is:

Code:

// VerilogA for pllphasenoise, vco, veriloga

`include "constants.vams"
`include "/home/wzliu/project/phase.vams" // from Listing 2, includes disciplines.vams.

module vco(in, out);
input in; output out;
voltage in;
phase out;
parameter real gain = 40e6 from (0:inf); // transfer gain, Kvco (Hz/V)
parameter real n = 1.32 from [0:inf); // white output phase noise at 1 Hz (rad2/Hz)
parameter real fc = 100K from [0:inf); // flicker noise corner frequency (Hz)
analog begin
Theta(out) <+ 2*`M_PI*gain*idt(V(in));
Theta(out) <+ flicker_noise(n, 2, "wpn") + flicker_noise(n*fc, 3, "fpn");
end
endmodule

Title: Re: how to build pll noise model based on verilog-a using Ken Kundert‘s method?
Post by lwzunique on Jan 19^th, 2017, 6:35pm

after i changed the veriloga of vco, I mean the parameter of n and fc, the single vco block can be simulated.
the result is as below.