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Design >> Analog Design >> Correct biasing scheme for Common Drain stage
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Message started by exp on Mar 23^rd, 2017, 7:54pm

Title: Correct biasing scheme for Common Drain stage
Post by exp on Mar 23^rd, 2017, 7:54pm

Hello,

I am struggling with the appropriate biasing scheme for a common drain stage (used as a buffer following a diff pair) in an advanced 28nm node. The following circuit shows the CD drain stage with P3a as active device and P12 as biasing current source and P4a and P14 is the biasing branch. The biasing current is injected via ib_buf.

In order to reduce Vth to a minimum, I use backbiasing of the PMOS transistor (supported by the technology). I also have the potential of the gate of the CD stage which I could use for biasing taken from a non-loading node, indicated by voc1r. (it is the common mode of the preceding diff pair obtained via a resistive divider).

I cannot use the same backbiasing voltage in the biasing branch because the VDS of P4a and P14 would get tiny, making the VDS of the biasing device under ib_buf (not shown) large and putting to much stress on it.

P3a and P12 have the same dimensions (318u/40n) and the biasing transistors P4a and P14 are 32u/40n. The anticipated current through P3a is 1.563mA, hence I force 156.3u through P14 and P4a.

As can be seen, ID with 18.3874m is off by an order of magnitude.

What is the proper biasing scenario for this setup?

I would expect not more than 20% mismatch in current ...

Thanks!
exp ...

Title: Re: Correct biasing scheme for Common Drain stage
Post by ULPAnalog on Mar 31^st, 2017, 9:12am

I think the problem is that the drain voltages of the pmos current mirrors are quite different, at least by 70mV and in this smaller scale process, expect Vds to have significant impact on Ids.

You should make sure the current mirror has near identical drain to source voltages to meet your requirement.

Title: Re: Correct biasing scheme for Common Drain stage
Post by rakshitdatta on Jul 29^th, 2017, 12:23pm

Seems to me that this is the backgate effect. The threshold voltages are different.

Title: Re: Correct biasing scheme for Common Drain stage
Post by Hercules Poirot on Aug 8^th, 2017, 5:00am

P4a and P12 have completely different threshold voltages because of back biasing. To get a proper current mirror, make sure you use devices of the same threshold.
P.S. Which process is this?

Title: Re: Correct biasing scheme for Common Drain stage
Post by Berti-2 on Aug 10^th, 2017, 3:50am

Hey Hercules Poirot,

To me the schematic symbols look familiar: Global Foundries 28nm? ;-)

You are definitely right: With different voltage at the bulks, this is for sure not a proper current mirror.