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Design Languages >> Verilog-AMS >> Modelling DAC non linearity using look up table
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Message started by subtr on Mar 29^th, 2017, 10:37pm

Title: Modelling DAC non linearity using look up table
Post by subtr on Mar 29^th, 2017, 10:37pm

Hi,

I would like to represent a non linear DAC using a verilogA block. Fundamentally, I would like to read a file where I have 8 bit code as first column and get the corresponding real number from column two and pass it to a real variable in my code. Since it's discrete look up table, interpolation is not required. Could anyone give a sample example with the function which is capable of doing this?

Thanks

Title: Re: Modelling DAC non linearity using look up table
Post by Andrew Beckett on Mar 30^th, 2017, 12:36am

Have you looked at the $table_model function? That should do what you want...

Regards,

Andrew.

Title: Re: Modelling DAC non linearity using look up table
Post by ULPAnalog on Mar 31^st, 2017, 9:07am

Hi Andrew

Thanks for the information on $table_model. I was wondering if this was a more recent addition to the standard as I do not see it mentioned in Ken's book on Verilog AMS.

Best regards

Title: Re: Modelling DAC non linearity using look up table
Post by Geoffrey_Coram on Apr 5^th, 2017, 5:01am

Indeed, I see that Ken's book references version 2.1 of the Verilog-AMS language reference manual. I got involved with VAMS after 2.2 was released, which has $table_model. Now we're on 2.4; Ken's book could do with an update!

Title: Re: Modelling DAC non linearity using look up table
Post by Andrew Beckett on Apr 6^th, 2017, 1:37pm

Although as version 2.2 of the LRM came out in November 2004 (i.e. over 12 years ago), it's hardly a recent addition to the language! Unfortunately it missed Ken and Olaf's book by a few months...

Andrew.