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Design Languages >> Verilog-AMS >> Accessing Global Variables in verilogA
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Message started by subtr on Apr 14^th, 2017, 3:32pm

Title: Accessing Global Variables in verilogA
Post by subtr on Apr 14^th, 2017, 3:32pm

I would like to know if it's possible to access the global variables in verilogA when I run a simulation. The uses are as follows :

1) variables can be used to change the internal parameters of the verilogA so that it can adapt to the settings without passing any voltage or current through a port which represents the change of variable. Sometimes the variable can be a delay, bit pattern or a frequency variable which could be difficult to pass to the verilogA file.

2) If the verilogA file is used for punching out data from a simulation into a file which is to be processed later on, the user has to run the simulations in series in case of corner simulations because the file gets over written. But if variables can be accessed in the verilogA, then it can be used as a string to modify the file name which enables user to run cross corner simulations in parallel. :)

I'm looking for a way to achieve the second option which would only be possible if verilogA file can access the variables.

Title: Re: Accessing Global Variables in verilogA
Post by Andrew Beckett on Apr 16^th, 2017, 12:09am

If this is Veriog-A (rather than AMS) and the simulator is spectre, the best thing to do is make the variable a parameter to your model and then pass the global (design) variable on the instance of the model.

If it is Verilog-AMS and the simulator is AMS Designer, you can reference variables as cds_globals.varName .

If it's another simulator, probably best if you state which simulator you're using...

Regards,

Andrew.