The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Regarding issue with absdelta
https://designers-guide.org/forum/YaBB.pl?num=1495975077

Message started by AMS_ei on May 28^th, 2017, 5:37am

Title: Regarding issue with absdelta
Post by AMS_ei on May 28^th, 2017, 5:37am

Hi,

I am trying to achieve electrical to real conversion using "absdelta".
Here is my code:

//code starts here/////////
module elec2real(signal);
input signal;
electrical signal;

real sig_vol;

initial begin
sig_vol = 0;
end
always @(absdelta(V(signal), 0.01)) begin
sig_vol = V(signal);
end

endmodule

//Code ends here///////////////

The issue is that when V(signal) is 0V, sig_vol is driven to -4.44089e-16 as shown in the attached file.

Could anyone please explain me how can I resolve this issue?

Thank you.

Kind regards.

Title: Re: Regarding issue with absdelta
Post by AMS_ei on May 28^th, 2017, 6:21am

The waves of V(signal) and sig_vol is attached

Title: Re: Regarding issue with absdelta
Post by Ken Kundert on May 28^th, 2017, 4:30pm

What issue? Are you concerned with a difference of less than a fV?

-Ken

Title: Re: Regarding issue with absdelta
Post by AMS_ei on May 29^th, 2017, 8:48pm

Hi Ken,

Thank you for your interest
I am bit concerned about its -ve value.
I was expecting a +ve value (may be in the order of fV) but, it should be +ve.
Is it possible to obtain that?

Thank you.

Kind regards.

Title: Re: Regarding issue with absdelta
Post by Ken Kundert on May 30^th, 2017, 12:08am

Simulators cannot provide the accuracy you are looking for. There is always a small amount of uncertainty in the result.

-Ken