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Message started by ocmob on May 28th, 2017, 7:56am

Title: AMS digital edges model
Post by ocmob on May 28th, 2017, 7:56am

I know this is a forum for analog designers. Right now i deal with digital design but this is a question considering a property of Cadence AMS simulator.

I am currently designing an adder circuit and I use AMS to connect digital SystemVerilog testbench with transistor level adder schematic. Technology file is UMC180. When I decrease clock period close to 1 ns (clock is generated form SystemVerilog testbench) waveform becomes more and more trapezoidal. (clock edges become less and less steep). The clock is driving two transistor level flops. There I have a question: how does the AMS model a digital SystemVerilog output? Is it an ideal current source with a fixed current? Loading flop input capacitance with constant current would explain this behaviour. What should I do to make the edges more steep - is it even possible?

Thanks for any help.

Title: Re: AMS digital edges model
Post by Andrew Beckett on May 28th, 2017, 10:02am

This depends on the settings you have chosen for your connect rules (which controls how digital to analog and vice versa is handled). If using ADE, this would be handled via Setup->Connect Rules/IE Card.

I suggest you read the documentation for more details or run through the tutorial - giving a full AMS tutorial here is not really practical!

Kind Regards,


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