The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> CMRR effects of error amp in LDO
https://designers-guide.org/forum/YaBB.pl?num=1497159151

Message started by leejooseong222 on Jun 10^th, 2017, 10:32pm

Title: CMRR effects of error amp in LDO
Post by leejooseong222 on Jun 10^th, 2017, 10:32pm

hi

i wonder the effects of low CMRR error amp in LDO

low CMRR can generate offset, but i think some offset in LDO doesnt make that large issue.

and large W/L can lower the offset

what do you guys think?

+ does low CMRR make common mode positive feedback? if that, how can i simulate that stb??

Title: Re: CMRR effects of error amp in LDO
Post by tzg6sa on Jun 11^th, 2017, 12:58am

I argue your statement that offset is not a problem in an LDO, since it stands for low-drop-out. For say 150mV dropout even 20mV is a lot. If you have enough dropout to waste through your pass device, then the right term would be voltage regulator.

Large W/L might reduce your input offset, but not your output one. You should isolate your signals from the supply rails.

Otherwise since your common mode range is fixed by a low resistance voltage reference - I am just guessing here - and it will not be tuned in a wide range, CMRR has little sense to me. Of course I also assume that there is no ground reference between your feedback divider and your reference.

Title: Re: CMRR effects of error amp in LDO
Post by leejooseong222 on Jun 11^th, 2017, 4:20am

thank you for reply

actually i made voltage regulator for low supply application (under 0.5v)

so i employed 4 TR error amp (pseudo amplifier, 5 TR basic single ended amp without tail current)

all TR operates in sub treshold so WL sizes are very big ( tens um range)

the error amp has very poor CMRR, but when i did monte carlo simulation, the maximum offset was under 5 mV (offset = reference voltage - output volatge)

loop performance : DC gain is higher than 20 db, PM is larger than 50 deg.

i think these are enough performances for my application, but measured results were not good.

now i debug, the poor CMRR would make the problem... the simulation could not catch the common mode issues(common mode positive feedback...etc..)

what eles can i think or simulate?....