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Design >> Analog Design >> PVT of nulling resistor in miller compensation.
https://designers-guide.org/forum/YaBB.pl?num=1501060268

Message started by Jacki on Jul 26^th, 2017, 2:11am

Title: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 26^th, 2017, 2:11am

Hi,

Nulling resistor is a common way to compensate the RHP zero in the two-stage miller compensation opamp. How to handel the PVT variation of the nulling resistor in a robust design? Except for trimming the nulling resistor, are there any advanced solution to do it? From my own opinion, I don't like to use the gm of a transistor as the nulling resistor (maybe I am wrong). Any comments? Thank you.

Title: Re: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 26^th, 2017, 3:52am

Also we can use a common gate circuit, a voltage buffer, or a current mirror buffer to block the feedthrough path and avoid the zero on RHP. But I don't understand why we will reduce the swing if voltage buffer is used.
Could anybody recommend some papers on the different types of the miller compensation?
Thank you.

Title: Re: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 26^th, 2017, 4:50am

If we consider a source follower as the voltage buffer, I think it has the input voltage range, which may limit the output swing if the swing is too large.

Title: Re: PVT of nulling resistor in miller compensation.
Post by DanielLam on Jul 26^th, 2017, 12:23pm

We use a transistor's 1/gm as the resistance because we are trying to match another FET's gm. Check the pole-zero cancellation equation. I think you are missing a key idea here.

In CMOS, the nulling resistor a FET in triode. This takes care of process, and temperature (if you do the layout right). For voltage, you can use a couple FET Vgs drops to match the 2nd stage FET. Sometimes for power reduction, the triode FET gate will be biased to Vdd.

This is a well-known technique, and is published in many textbooks such as Razavi, Johns & Martins, or you can even just google search.

Title: Re: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 27^th, 2017, 1:46am

Hi DanielLam,

Thank you for your reply. I know some designers like to use the gds to generate the nulling resistor, but the transistor is normally biased at triode region. However the gm of the second stage input transistor is in saturation region. I would guess it is difficult to get a maching gm when two transistors are biased in different modes, especially with PVT. In theory I think it would work, but in practice it might not be easy. If just using a nulling resistor, I would prefer the poly resistor, just wonder if there is any advanced solution to tune the value of the resistor covering the PVT for both resistor and the gm of the input transistor of the second stage.
Of course we can easily block the feed throught path to eliminate the zero by a CG stage. Just thinking how to compensate the PVT if a poly resistor is used as the nulling resistor.

Title: Re: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 27^th, 2017, 7:50am

In theory, the gds in triode region is the same as the gm in saturation region when over drive voltage is the same. But normally the Vgs of the input transistor in the second stage is not a copy voltage from the current mirror, and it is difficult to generate a same Vgs for the triode-region transistor, hereby the compensation is not very accurate. I know using the common gate transistor to block the path is very attractive. Still want to know if any good solution to compensate the PVT of a poly resistor and gm.
Thank you for your time.

Title: Re: PVT of nulling resistor in miller compensation.
Post by DanielLam on Jul 27^th, 2017, 8:56am

First, I'll say I've monte-carlo'ed and sweep power + temperature on a 2 stage opamp with poly SI, and triode FETs as the nulling FET. If memory serves, the nulling FET was always better in schematic (you can mess up in layout). Matching a gm to a R should be worse than matching a gm to a gm.

Second, the remaining non-idealities are short channel effects.

Third, I think this statement is wrong

" But normally the Vgs of the input transistor in the second stage is not a copy voltage from the current mirror, and it is difficult to generate a same Vgs for the triode-region transistor,"

There are well-published ways to have those two transistors have the same Vgs. Razavi or Johns and Martin have a circuit you can directly use to do this.

I'm not replying anymore until you take a look at the textbook.

Title: Re: PVT of nulling resistor in miller compensation.
Post by Jacki on Jul 28^th, 2017, 12:56pm

Hi DanielLam,

Thank you for your info. I look at the book chapter "compensation". You are right, I think the figure 10.32 in Razavi's book is what I would like to think, because even the output swing is large, it is not a big deal in this case.