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Design >> High-Speed I/O Design >> Testing a High Speed Differential TIA
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Message started by repah on Aug 9^th, 2017, 11:42am

Title: Testing a High Speed Differential TIA
Post by repah on Aug 9^th, 2017, 11:42am

I am designing a broadband amplifier in CMOS - it is a transimpedance amplifier (TIA) - and it is differential (running at 40gb/s with a bandwidth of about 0.7 * 40 gb/s = 28 GHz).

I am wondering about the testing of differential high speed amplifiers using S parameters in the Cadence Spectre ? What would the test bench look like ? Would I use a balun ?

The input is a current from a photodiode since this is for optical applications.

It is a simple shunt feedback TIA but driven differential - I have attached a picture.

Title: Re: Testing a High Speed Differential TIA
Post by Ken Kundert on Aug 11^th, 2017, 10:21am

The testbench is a simplified model for the 'rest of the circuit' or the circuit with the DUT removed. You are asking about the testbench but showing us the DUT. If you want help on the testbench, you have to tell us about the rest of the circuit. Specifically, how are you going to drive the inputs and load the outputs.

-Ken

Title: Re: Testing a High Speed Differential TIA
Post by repah on Aug 26^th, 2017, 5:23pm

Hello,

I am driving it with a photdiode, with an associated capacitance - so that would be a current source.

At the output would be another amplifier stage, most likely a limited amplifier - which is a differential pair - a few stages of differential pairs - for gain.

Thank you.