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Design >> RF Design >> Ground plane in silicon cmos rf design
https://designers-guide.org/forum/YaBB.pl?num=1503451350

Message started by engrvip on Aug 22^nd, 2017, 6:22pm

Title: Ground plane in silicon cmos rf design
Post by engrvip on Aug 22^nd, 2017, 6:22pm

Hi

I am designing 1.1GHz lna in silicon cmos technology. Is ground plane required for design at this frequency. If yes, should this ground plane be accessed from package plane using TSV ( through silicon via) or one of lower metal layers in stack can be used for this purpose.

Regards
Engrvip