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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Fully Differential Opamp MacroModel in Cadence https://designers-guide.org/forum/YaBB.pl?num=1503793304 Message started by repah on Aug 26th, 2017, 5:21pm |
Title: Fully Differential Opamp MacroModel in Cadence Post by repah on Aug 26th, 2017, 5:21pm I am trying to design a fully differential opamp (infinite gain, infinite bandwidth) with Cadence to simulate a Discrete Time Sigma Delta Modulator at the system level. What is best to use ? A Verilog model ? or Controlled sources - VCCS etc. Does anyone have any examples of controlled source model macromodels for a fully differential opamp ? Thank you. |
Title: Re: Fully Differential Opamp MacroModel in Cadence Post by davidshw on Aug 28th, 2017, 6:25pm here is a verilog-a model for you reference. Code:
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Title: Re: Fully Differential Opamp MacroModel in Cadence Post by Geoffrey_Coram on Sep 5th, 2017, 6:01am Hi, davidshw - Thanks for posting that code. I'd recommend a few tweaks: - combine the port declarations: output VOP, VOM; input VP, VM, VCM, VDD, VSS; electrical VOP, VOM, VP, VM, VCM, VDD, VSS; - remove the "@initial_step" condition: instead of @ ( initial_step or initial_step("dc") ) begin cc=1p; // compensation cap co1 = 1f ; //1st stage output cap co2 = 1f ; //2nd stage output cap just have begin cc=1p; // compensation cap co1 = 1f ; //1st stage output cap co2 = 1f ; //2nd stage output cap Otherwise the simulator may think it needs to set up special storage to handle remembering those values from timepoint to timepoint. It actually seems to me that those capacitance values ought to be parameters rather than hard-coded numbers. |
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