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Design >> Analog Design >> How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
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Message started by hezea on Sep 15^th, 2017, 8:57pm

Title: How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
Post by hezea on Sep 15^th, 2017, 8:57pm

How to design a CPPLL with a cycle to cycle jitter less than 300ps, the frequency of the CPPLL is 10MHz to 200MHz.
And how to simulate the cycle to cycle jitter of the CPPLL, my simulation software is the spectre, the calculator have no function to measure the cycle to cycle jitter.

Title: Re: How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
Post by Berti-2 on Sep 19^th, 2017, 12:14am

Unfortunately, I will not be able to provide you a cookbook recipe how to design a PLL .... but cycle jitter you can simulate either using:

1.) pnoise analysis (will only work for the sub-blocks like VCO and not the entire PLL)

2.) transient noise and period_jitter function in calculator. Even though transient noise simulation of the full PLL might be challenging (combination of high frequency in VCO but low frequency time constants in loop)

I would suggest you to read some papers about PLL with similar specs you are aiming for.

Title: Re: How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
Post by hezea on Sep 23^rd, 2017, 9:37pm

thangks for your answer, I have a question recently, what is the relationship between the period_jitter and cycle to cycle jitter? Is it the 1.414 times relationship ?

Title: Re: How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
Post by Berti-2 on Sep 25^th, 2017, 11:56pm

Period jitter is the difference between the actual period and the ideal reference period.
Cycle to cycle jitter is the difference between period i+1 and period i.

Cycle to cycle jitter is more suitable for measurements than period or edge jitter as you don't need a reference (the reference is the previous period). However, you should keep in mind that for low frequency jitter, the clock edges might be correlated. This low frequency jitter is then not considered in period or cycle-to-cycle jitter.
TIE (time interval error) jitter is also often used, as it can conveniently be measured with a scope.

I guess it depends on your system which kind of jitter is of interest.