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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> DNL/INL calculation using histogram testing of sinusoidal input https://designers-guide.org/forum/YaBB.pl?num=1512848255 Message started by niloun on Dec 9^{th}, 2017, 11:37am |
Title: DNL/INL calculation using histogram testing of sinusoidal input Post by niloun on Dec 9^{th}, 2017, 11:37am Hi everyone, I want to calculate DNL and INL of a SAR ADC and I have read almost every thread about this subject on this forum and other websites, but I couldn't find a good answer to my question. As you know three main methods have been proposed for DNL/INL calculation, including Maxim's code for DNL/INL, Boris Murmann's code and using a hdiLb Verilog code. Many have suggested not to simulate DNL/INL because it will take a long time to have 99% accuracy. Reading these methods, to me, it sounds that for the histogram test, simulation time for the ramp input will be an issue and a big number of inputs are necessary (nearly 100 samples per code) but no one has mentioned anything about input sine waves. All in all, what are the considerations if I want to use histogram testing using sinusoidal input? and how many samples are enough when using a sine wave to have a reasonable accuracy? Thanks in advance, |
Title: Re: DNL/INL calculation using histogram testing of sinusoidal input Post by DanielLam on Apr 4^{th}, 2018, 10:16pm I'm 4 months late to see this, but I'll answer since no one has. There are some statistics on how meaningful a DNL/INL calculation is given a certain sample size and confidence level. To have a high confidence level, and high resolution (10+), you might need more than a million points. That's why people say not to simulate it. I have simulated DNL/INL before for lower resolutions. I did some spot checking to see if 10-20 points proved decent enough to see the effect I wanted. For these sims to be manageable, you need to set everything else ideal except the error you are looking at. In my case, I was looking at a MSB mismatch in the capacitor array of an ADC. With my ideal sim, to get ~4k points, it probably less than 30 minutes. If you want faster, go to Matlab or some other language. Regarding the input, a sine wave is probably used more than a ramp generator. I've helped design a few ADCs, and we've never used a ramp generator. The reason is that you can easily make good pure sine wave with a filter. Finding a good ramp generator is a lot harder. I think the old story is that in the past, it was really hard or expensive to find good filters. So people used ramp generators. But nowadays, you can find good filters pretty cheaply, and the situation has changed. By the way, to be "technically" correct, you will need more points for the sine wave test because there will be more sampled points at the mins and maxes, rather than in the middle of the sine wave. How many samples to use? Depends on what resolution your ADC is, and how big the error you make. You can trade error with # of points or resolution. I've probably settled to around 10 points per code in the past. I'd suggest trying it out in Matlab with ideal ADCs, and seeing for yourself. I definitely look at INL/DNL in my Matlab models, and it's fast. Cadence INL/DNL is definitely one of the last things to try. |
Title: Re: DNL/INL calculation using histogram testing of sinusoidal input Post by niloun on Apr 5^{th}, 2018, 9:25am DanielLam wrote on Apr 4^{th}, 2018, 10:16pm:
Thank you so much for the complete answer. |
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