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Design Languages >> Verilog-AMS >> help with array and loop in verilog-A
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Message started by Shahriar on Dec 21^st, 2017, 12:27pm

Title: help with array and loop in verilog-A
Post by Shahriar on Dec 21^st, 2017, 12:27pm

Hi,

I'm writing a verilog-A code for a block. So far, the code should only make two arrays that are binary equivalents of two input decimal numbers.

Code:

// VerilogA for veriloga_lib, scratch, veriloga

`include "constants.vams"
`include "disciplines.vams"

module scratch (out);

output out;
electrical out;
parameter integer nbits = 7 from [0:32];
parameter integer data1 = 11 from [0:((2**nbits)-1)];
parameter integer data2 = 85 from [0:((2**nbits)-1)];

integer data1bits[(nbits-1):0], data2bits[(nbits-1):0], temp[(nbits-1):0];
integer clk_state, i, temp_data;

analog begin

temp_data = data1;
for (i=0; i<nbits; i=i+1) begin
data1bits[i] = temp_data%2;
temp_data = temp_data/2;
$strobe("data1bits[%d] = %d",i,data1bits[i]);
end
temp_data = data2;
for (i=0; i<nbits; i=i+1) begin
data2bits[i] = temp_data%2;
temp_data = temp_data/2;
$strobe("data2bits[%d] = %d",i,data2bits[i]);
end

end

endmodule

If I instantiate it a schematic and do a simulation, say dc, it finishes fine and prints the values, as I want them, in the output log. This is what it looks like.

Quote:

****************
DC Analysis `dc'
****************

Opening the PSF file ../psf/dc.dc ...
Important parameter values:
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 25 C
tnom = 25 C
tempeffects = all
gmindc = 1 pS
data1bits[0] = 1
data1bits[1] = 1
data1bits[2] = 0
data1bits[3] = 1
data1bits[4] = 0
data1bits[5] = 0
data1bits[6] = 0
data2bits[0] = 1
data2bits[1] = 0
data2bits[2] = 1
data2bits[3] = 0
data2bits[4] = 1
data2bits[5] = 0
data2bits[6] = 1
Convergence achieved in 2 iterations.
Total time required for dc analysis `dc': CPU = 3.999 ms, elapsed = 11.43 ms.
Time accumulated: CPU = 303.952 ms, elapsed = 1.10687 s.
Peak resident memory used = 52.3 Mbytes.

modelParameter: writing model parameter values to rawfile.

But if I comment out the lines with $strobe command, simulation returns an error.

Quote:

Error found by spectre during initial setup.
ERROR (ASL-5401): "/projects/ibm/csoi7sw/AD1178RX/work_libs/sj028179/cds/veriloga_lib/scratch/veriloga/veriloga.va" 21: I7: Array access out of bounds near line number 21. Correct the problem and try again.

Line 21 is is "data1bits[i] = temp_data%2 in the code.

Could anyone please help me figure out what I am doing wrong?

Also, is there any way to print an array in verilog-A, instead of going to the elements one by one?

Thanks.

Shahriar

Title: Re: help with array and loop in verilog-A
Post by Andrew Beckett on Dec 21^st, 2017, 11:34pm

It doesn't do that for me - if I comment out the $strobe lines it works fine. I didn't spot anything wrong with the models.

Which spectre version are you using (what does it say at the top of the log file)?

There's no way to print the whole array in one go - you need a loop such as you're doing.

Regards,

Andrew