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Design Languages >> Verilog-AMS >> synthesize verilog-a
https://designers-guide.org/forum/YaBB.pl?num=1514834038

Message started by vaibhav16119 on Jan 1^st, 2018, 11:13am

Title: synthesize verilog-a
Post by vaibhav16119 on Jan 1^st, 2018, 11:13am

Hello all,

I am working with verilog-a. I am simulating a verilog-a code in Cadence virtuoso. Now, I want to synthesize that code.
Please help me out.

Title: Re: synthesize verilog-a
Post by Andrew Beckett on Jan 2^nd, 2018, 1:47am

To synthesise Verilog-A you need a circuit designer (i.e. a human).