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Simulators >> Circuit Simulators >> doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
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Message started by blue111 on Jan 27^th, 2018, 5:50pm

Title: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by blue111 on Jan 27^th, 2018, 5:50pm

I have created a series, shunt LC bandstop/notch filter.

https://github.com/promach/frequency_trap/tree/9806e6c293463c1eca3b1b5f0c92ac3e76d14f28

The screenshots above correspond to frequency_trap.net, CMOS_Inverter.net and Gm2.net respectively.

However, when I run "make clean && make" after cloning the project from github, ngspice gave me the following error:

Quote:

doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with p1-instance m.x1.m4
tran simulation(s) aborted

Could anyone advise ?

CMOS_Inverter.net

Code:

* gnetlist -L ../.. -g spice-noqsi -o CMOS_Inverter.net CMOS_Inverter.sch
* SPICE file generated by spice-noqsi version 20130710
* Send requests or bug reports to jpd@noqsi.com
.subckt INV1 2 1
M4 1 2 Vdd Vdd P1 l=0.4 w=3 m=25
M1 1 2 Vss Vss N1 l=1.2 w=3 m=25
*
*
.ENDS

frequency_trap.net

Code:

* gnetlist -L ../.. -g spice-noqsi -o frequency_trap.net frequency_trap.sch
* SPICE file generated by spice-noqsi version 20130710
* Send requests or bug reports to jpd@noqsi.com
Ctest X1.IN Vout 1n
Vd Vdd GND 'SUPPLY'
Vs Vss GND 0V
.GLOBAL Vdd Vss
.INCLUDE CMOS_Inverter.net
.INCLUDE Gm2.net
.INCLUDE active_inductor.net
.PARAM SUPPLY=3.3v
.options TEMP=25
.MODEL n1 NMOS
.MODEL p1 PMOS
Vtest Vtest GND dc 0
+ac 1
CL GND Gm2.IN 0.07pF
XGm2 Gm2.IN Gm2.OUT GM2
X1 X1.IN X1.OUT INV1
V_IP_X1 X1.OUT Gm2.IN DC 0V
V_IP_Gm2 Gm2.OUT X1.IN DC 0V
Rs Vtest Vout 1e99 ac=1e-6
.control
op
ac lin 10000 138 200
write frequency_trap.raw
gnuplot vtest db(vtest)
gnuplot vout db(vout)
*plot Vtest Vout
tran 0.1p 400p
plot Vtest X1.IN X1.OUT
setplot
plot i(v.xgm2.v_ip3) i(v.xgm2.v_ip4) i(v.xgm2.v_ip5) i(v.xgm2.v_ip6)
noise v(Vtest) Vtest lin 100 1 10G
setplot noise1
let noise_figure=db(inoise_spectrum)/2-db(2*sqrt(boltz*290*50))
plot noise_figure
.endc

Gm2.net

Code:

* gnetlist -L ../.. -g spice-noqsi -o Gm2.net Gm2.sch
* SPICE file generated by spice-noqsi version 20130710
* Send requests or bug reports to jpd@noqsi.com
.subckt GM2 7 3
M4 g3 g3 1 1 P1 l=1u w=3u
M3 3 g3 2 2 P1 l=1u w=3u
M5 3 5 4 Vss N1 l=1u w=3u
M6 g3 7 6 Vss N1 l=1u w=3u
I2 8 Vss 40uA
I1 9 Vss 40uA
Vb 5 Vss 1.8V
Rs 9 8 500k
*
*
V_IP6 6 8 DC 0V
V_IP5 4 9 DC 0V
V_IP4 Vdd 1 DC 0V
V_IP3 Vdd 2 DC 0V
.ENDS

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by Andrew Beckett on Jan 28^th, 2018, 12:23am

I'm not familiar with the tools you're using (you didn't even say what they were - which isn't very helpful for anyone trying to help).

However, one glaring problem is that the transistors in the inverter are probably a million times too big - the dimensions are in metres and so the transistors in the inverter have w=3 metres and l=0.4 metres, compared with those in the gm block which are in um. That can't help and presumably is incorrect.

Also, not sure if there's supposed to be such a huge resistance Rs (1e99 - effectively open circuit) or not?

Regards,

Andrew.

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by blue111 on Jan 28^th, 2018, 5:11am

I am using gschem with noqsi backend and ngspice simulator.

I have corrected the dimension of the inverter to um.

Regarding the huge DC Rs, let me ponder a little bit more.

If I use Rs = 1e-6 both in transient and AC analysis, I have no more transient simulation error and I am getting the following voltage plots.

Do you have any clue why the CMOS inverter input and output differ by around 0.3V ?

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by Andrew Beckett on Jan 29^th, 2018, 8:03am

Well, M3 and M4 in the GM block are both conducting a considerable amount of current, causing the voltages to drop - I didn't try to debug your circuit, but it doesn't really work... I think that's something for you to investigate - take a look at the operating point of the devices, and see what's going on.

I don't have access to the tools you're using, so I improvised with a different simulator.

Your transistor models are also probably rather sensitive to the defaults in the simulator you're using - you've not provided any parameters at all. Doubt that's the reason for the problem - it's probably the circuit itself.

Andrew.

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by blue111 on Jan 29^th, 2018, 11:40am

Quote:

I didn't try to debug your circuit, but it doesn't really work... I think that's something for you to investigate - take a look at the operating point of the devices

In ngspice, .OP gave me the following:

I am looking at it now. Do you have any comment ?

Quote:

Initial Transient Solution
--------------------------

Node Voltage
---- -------
x1.in 2.09899
vout 0
vdd 3.3
vss 0
vtest 0
gm2.in 1.8
xgm2.g3 2.14857
xgm2.1 3.3
gm2.out 2.09899
xgm2.2 3.3
xgm2.5 1.8
xgm2.4 0.649101
xgm2.6 0.649101
xgm2.8 0.649101
xgm2.9 0.649101
x1.out 1.8
v_ip_gm2#branch 0
v_ip_x1#branch 0
v.xgm2.v_ip3#branch 4e-05
v.xgm2.v_ip4#branch 4e-05
v.xgm2.v_ip5#branch 4e-05
v.xgm2.v_ip6#branch 4e-05
v.xgm2.vb#branch 0
vtest#branch 0
vs#branch 0.00280043
vd#branch -0.00280043

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by Ken Kundert on Jan 31^st, 2018, 12:30pm

The circuit seems to be operating as I would expect. There is no reason why the input and output voltages of the inverter should not differ by 300mV. Why does this difference bother you?

What kind of circuit is this? An amplifier? A latch? An oscillator?

The weird resistor (1e99Ω in dc, 1μΩ in ac) is just asking for trouble from the simulator and is completely unnecessary. It is in series with a capacitor, which already acts like an open circuit in DC.

-Ken

Title: Re: doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with
Post by blue111 on Jan 31^st, 2018, 6:32pm

@Ken

It is derived from http://www.seas.ucla.edu/brweb/papers/Conferences/LK_ISSCC15.pdf

However, I could not obtain the desired inductor value from the gyrator made up of X1 and GM2 circuit blocks.

If all resorts failed, I am thinking of using S-parameter to check the value of the active inductance created from gyrator structure consisting of CMOS inverter and GM2 circuit blocks.

Besides, I have already use a much smaller Rs instead 1e99.