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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Load limit on the TIEHI and TIELO cells https://designers-guide.org/forum/YaBB.pl?num=1517974578 Message started by pkd on Feb 6th, 2018, 7:36pm |
Title: Load limit on the TIEHI and TIELO cells Post by pkd on Feb 6th, 2018, 7:36pm When I see the .lib of a TIEHI or TIELO cell, I see some maximum capacitance load limit at the output pin. Since there is no transition requirement for this cell, I am wondering why does this limit exist and how is this limit calculated. The TIEHI cell is nothing but a diode connected PMOS, source connected to VDD, drain/gate connecting to the gate of an NMOS. Source of the NMOS at ground, drain to the gate of a PMOS whose source is VDD and drain is out output pin. |
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