The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> LDMOS voltage tolerance
https://designers-guide.org/forum/YaBB.pl?num=1523162218

Message started by neoflash on Apr 7^th, 2018, 9:36pm

Title: LDMOS voltage tolerance
Post by neoflash on Apr 7^th, 2018, 9:36pm

In deep sub-micron process, usually LDMOS can be used for higher voltage tolerance.

With drain extension, it is understood that Vds tolerance can be increased.

However, why Vgd tolerance is also increased?

For example, in 40nm process 3.3v oxide, LDMOS Vgd can tolerate 5V?

I don't understand why Vgd (involving oxide) can be increased when there is no current?

Title: Re: LDMOS voltage tolerance
Post by Jacki on Apr 10^th, 2018, 11:35pm

I have the similar question, for my experience, with the same IO transistor, when I increase the channel length, the gate voltage can be increased as well, for example from 1.8V to 3.3V. But the gate oxide thickness seems not increase.