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Design >> High-Power Design >> LDMOS in DNW
https://designers-guide.org/forum/YaBB.pl?num=1528484739

Message started by neoflash on Jun 8^th, 2018, 12:05pm

Title: LDMOS in DNW
Post by neoflash on Jun 8^th, 2018, 12:05pm

Can TSMC LDMOS bulk be a separate P-well and tied to its own source, to reduce body effect? Like a traditional MOSFET?

Thanks.

Title: Re: LDMOS in DNW
Post by Geoffrey_Coram on Jun 15^th, 2018, 8:43am

That's probably proprietary information that the foundry won't want on a public web site. You should probably contact the foundry (or read the documentation for whatever process it is that you're using).

Title: Re: LDMOS in DNW
Post by Horror Vacui on Jun 17^th, 2018, 12:40pm

I see no theoretical obstacles, that's why you have DNW in the technology. What is the source of your doubt? If you run a simulation with the most equipped model and spectre throws an assert/warning about it, than it has a reason. People has taken extra efforts to add these checks into the model file. Especially if the model maturity is high.