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Design >> Analog Design >> Post-layout simulation of sigma-delta modulators "error"
https://designers-guide.org/forum/YaBB.pl?num=1535058485

Message started by PCCDA on Aug 23^rd, 2018, 2:08pm

Title: Post-layout simulation of sigma-delta modulators "error"
Post by PCCDA on Aug 23^rd, 2018, 2:08pm

Hello,

I am designing a low-voltage SD modulator and I am having some troubles in post-layout simulation. I have performed the layout extraction with assura (RC - decoupled capacitances) and during the simulation (spectre with APS++ in conservative mode), the output DC level of the third active-RC integrator (there are only 3 integrators in the loop filter) did not set correctly, as can be seen in the attached figure. However, to my surprise, I tried the RC extraction setting the "coupled" capacitance option and the circuit works fine (the simulation time has increased as expected).

I already checked the CMFB loop stability and cannot see any problem. All schematic simulations, including PVT corners worked. Post-layout simulations before the top-level routing also worked well with RC extraction in decoupled capacitances mode.

Has anyone ever experienced a similar issue like this?

Regards.