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Design >> Analog Design >> effects of dummy metal fill parasitic capacitor on stability/Analog Design
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Message started by analog_design on Oct 14^th, 2018, 6:09am

Title: effects of dummy metal fill parasitic capacitor on stability/Analog Design
Post by analog_design on Oct 14^th, 2018, 6:09am

Hello,

I have question in relation to dummy fill density (tiling).

Does dummy fill parasitic capacitor affect stability of loop e.g. operational amplifier or LDO ?

Has anybody run post-layout simulation on extracted netlist with dummy metal fill ?

I know, It make difference in terms of interconnect delay and timing parameters to digital circuits or long paths ?