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Design >> Analog Design >> General method for phase-locked loop filter analysis and design
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Message started by blue111 on Oct 16^th, 2018, 9:09pm

Title: General method for phase-locked loop filter analysis and design
Post by blue111 on Oct 16^th, 2018, 9:09pm

For this http://sci-hub.tw/https://ieeexplore.ieee.org/document/4490229 General method for phase-locked loop filter analysis and design paper , I have few questions:

1) In section 3 Classification for PLLs , could anyone help to explain on this ? and how to derive this frequency roll-off expression ?

Quote:

The difference between order and type gives a measure of the ability to filter out high-frequency phase noise contribution, in such a way that the high-frequency roll-off is given by the expression: -6.02 * (order – type + 1) dB/octave.

2) Could anyone prove mathematically that "The order needs to be higher than type only when extra attenuation of phase noise is needed" ?

3) Besides, could anyone derive expression (7) ? and how does this inequality expression guarantee that the transient and filtering capabilities of the PLL is unchanged while increasing the hold range (which is proportional to K_pv, according to author ? ) ?

4) For Floyd Gardner's Phaselock Techniques 3rd edition book, how do we derive stability criterion inequality for type 3 digital PLL which is expression (4.23) ?