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Design >> Analog Design >> Clocking and Timing of SC Sigma Delta Modulator
https://designers-guide.org/forum/YaBB.pl?num=1542081985

Message started by repah on Nov 12^th, 2018, 8:06pm

Title: Clocking and Timing of SC Sigma Delta Modulator
Post by repah on Nov 12^th, 2018, 8:06pm

Hello,

Please see attached picture.

What is V in the clocking - ie. 2d/v and what is the timing of the reset clock ? When is the reset clock set, how long and why ?

Is is reset every OSR clock cycles ? Also isnt just setting an ideal capacitor with initial condition zero in simulation the same as setting a reset signal ?

Thank you.

Title: Re: Clocking and Timing of SC Sigma Delta Modulator
Post by polyam on Nov 13^th, 2018, 3:58pm

Hi,

V is the output of the delta-sigma and it needs to be fed back to the input to close the delta-sigma loop.
There are two main reasons to reset a delta-sigma modulator.
1- To lock up the ADC when the internal states get saturated.
2- To serve as a resettable ADC (well-known as incremental ADCs). In the incremental mode, the delta-sigma gets reset every OSR cycle and the ADC starts digitizing the next channel.

It's always nice to have reset signal even though the ADC is not going to be used in an Incremental mode. Otherwise, you need to play with supply voltage to lock up the ADC ;D!!!

Tnx

Title: Re: Clocking and Timing of SC Sigma Delta Modulator
Post by repah on Nov 13^th, 2018, 4:01pm

Okay, thank you.

Just to be clear, in incremental mode - the reset signal is sent every OSR cycles and how long is it set for ?

Is there a good reference on this - none of the existing sigma delta texts explain this very well.

Thank you.

Title: Re: Clocking and Timing of SC Sigma Delta Modulator
Post by polyam on Nov 13^th, 2018, 4:11pm

It's like this: you reset ADC (rst=1) and then reset is off. Wait for OSR cycle and then reset.

Have a look at "A low-power 22-bit incremental ADC"

Title: Re: Clocking and Timing of SC Sigma Delta Modulator
Post by polyam on Nov 13^th, 2018, 4:15pm

Also
Theory and applications of incremental /spl Delta//spl Sigma/ converters

Title: Re: Clocking and Timing of SC Sigma Delta Modulator
Post by repah on Nov 13^th, 2018, 4:57pm

Hello,

Thanks.

How about regular, non incremental Sigma Delta ADCs like this one:

When does that reset get set - thats a second order discrete time sigma delta ADC.

Thank you.