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Design >> High-Speed I/O Design >> jitter tolerance analysis in cadence
https://designers-guide.org/forum/YaBB.pl?num=1548337814

Message started by kazkou on Jan 24^th, 2019, 5:50am

Title: jitter tolerance analysis in cadence
Post by kazkou on Jan 24^th, 2019, 5:50am

Hi,
I am designing a clock and data recovery using cadence, I want to find the jitter toleance, but I have no ideal how to analysis in cadence, how to do the simulation ? or any guide or reference?
thank you.

Title: Re: jitter tolerance analysis in cadence
Post by Ken Kundert on Jan 25^th, 2019, 1:30pm

http://www.designers-guide.org/Analysis/bang-bang.pdf

Title: Re: jitter tolerance analysis in cadence
Post by kazkou on Jan 26^th, 2019, 7:48pm

Thank you for your reply sir.
Could u tell me where can I find for SONET specification(mask of Jtol and jitter mask etc..)? I found nothing on internet, only some brief information from wiki.