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Modeling >> Semiconductor Devices >> Verilog-A model extraction in ICCAP for Spectre
https://designers-guide.org/forum/YaBB.pl?num=1548809153

Message started by Ziauddin on Jan 29^th, 2019, 4:45pm

Title: Verilog-A model extraction in ICCAP for Spectre
Post by Ziauddin on Jan 29^th, 2019, 4:45pm

Hello,
I am extracting Verilog-A based model with ICCAP for spectre simulator.
This Verilog-a model is not within/built in Spectre simulator. So, the simulator is reading the Verilog-a model from my local directory.
Previously, when I have extracted other models like BSIM or PSP, those seem to much faster in terms of simulation time for extracting the model as the model were built in within the simulator.

Do, mmsim need to compile the verilog-a code each time it run the simulation or I can disable each running of the spectre.

Not sure, If I had explained it in details.

Thanks in advance.

Ziauddin

Title: Re: Verilog-A model extraction in ICCAP for Spectre
Post by Geoffrey_Coram on Jan 31^st, 2019, 7:12am

Generally, I think ICCAP is slower when it has to call out to an external simulator, compared to running the simulation internally. ICCAP does have Verilog-A capability, but I don't know if it needs an extra license (it did some years ago).
Most simulators that support Verilog-A do cache the compiled object. However, if the .va file is in a directory where you don't have write access, then the simulator may have trouble finding the compiled object from a previous run. You should try running Spectre outside of ICCAP and see whether it is able to re-use the compiled object, and/or look at the Spectre log file for the ICCAP simulations, which should report whether it is re-compiling the model or loading a pre-compiled object.
Also, you may want to reach out to Cadence to see if they have any suggestions for speeding up the simulation of Verilog-A compact models.

Title: Re: Verilog-A model extraction in ICCAP for Spectre
Post by vam on May 21^st, 2019, 2:53am

There might be serveral reasons:
1) Spectre needs to re-compile the VerilogA every time, you may follow Geoffrey_Coram's suggestion to check.
2) Some models need much calculation time. For example, if your Verilog-A model are basing on bsimcmg, then it should be slower than bsim4.
3) In most situation, the build-in models (bsim4, psp) of Spectre are optimized in internal nodes' connection. For example, if rs and rd are tiny, the intenral d/s node are shorted with external d/s node, but for Verilog-A model, most likely that a 0V vsource (V(d, di) <+ 0) are used, or a small resistor (1e-3) are added between internal and external nodes. So the build-in models need less iteration to get convergency (in fact, it needs no iteration when no internal nodes), while Verilog-A models needs more iteration.
4) The Verilog-A compiler in Spectre may be not so good. For example, a VerilogA bsim4 might be 3X slower than a build-in bsim4 in tran analysis. And if the compiler can't distinguish charge calculation from current calculation, the performance is more poor for DC, which may up to 6X slower.

Title: Re: Verilog-A model extraction in ICCAP for Spectre
Post by Geoffrey_Coram on May 21^st, 2019, 5:23am

Also make sure you're using a recent version of Spectre; if you have an older version, it may not compile as efficiently.