The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> High-Speed I/O Design >> BER measurement of CDR using Cadence
https://designers-guide.org/forum/YaBB.pl?num=1553107774

Message started by kazkou on Mar 20^th, 2019, 11:49am

Title: BER measurement of CDR using Cadence
Post by kazkou on Mar 20^th, 2019, 11:49am

HI,
I am new to Clock and data recovery, I need to design CDR from scratch.
I have some question for designing CDR.

Before we tapeout the chip, usually how to we know BER of our designed CDR? We get the BER through the simulation or we only need to get approximate value through calculation as described in "Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits" ?

How do we know the exact loop bandwidth of the CDR when doing pre-simulation(using cadence spectre/virtuoso) ?

Thank you

Title: Re: BER measurement of CDR using Cadence
Post by sheldon on Nov 29^th, 2019, 12:48am

Kazkou,

Assuming that the question is how to determine the value of the loop
bandwidth, equation #11. The values in the equation are the design values
of the blocks in the design. So in theory, you should be able to calculate
the BER from the initial design studies. The values of Kpd and H(f) should
be fixed. The value of Kvco maybe a challenge since control voltage to
frequency transfer function maybe non-linear. However, in most cases
this relationship is controlled by the VCO calibration and should effectively
be a constant also.

Sheldon