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Design >> High-Speed I/O Design >> BER measurement of CDR using Cadence
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Message started by kazkou on Mar 20th, 2019, 11:49am

Title: BER measurement of CDR using Cadence
Post by kazkou on Mar 20th, 2019, 11:49am

HI,
I am new to Clock and data recovery, I need to design CDR from scratch.
I have some question for designing CDR.

Before we tapeout the chip, usually how to we know BER of our designed CDR? We get the BER through the simulation or we only need to get approximate value through calculation as described in "Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits" ?

How do we know the exact loop bandwidth of the CDR when doing pre-simulation(using cadence spectre/virtuoso) ?

Thank you

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