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Modeling >> Behavioral Models >> VerilogA-instantiation of array of modules using looping structure
https://designers-guide.org/forum/YaBB.pl?num=1556048372

Message started by Anish on Apr 23^rd, 2019, 12:39pm

Title: VerilogA-instantiation of array of modules using looping structure
Post by Anish on Apr 23^rd, 2019, 12:39pm

I am developing a model for an array of delay cells to be used for a time-to-digital converter. I am trying to replace the following module instantiations with a looping structure-

delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(143)) dly_up1 (up_buf,delay_chain_up[1], delay_ctrl[1]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(243)) dly_up2 (up_buf,delay_chain_up[2], delay_ctrl[2]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(123)) dly_up3 (up_buf,delay_chain_up[3], delay_ctrl[3]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(7)) dly_up4 (up_buf,delay_chain_up[4], delay_ctrl[4]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(9)) dly_up5 (up_buf,delay_chain_up[5], delay_ctrl[5]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(11)) dly_up6 (up_buf,delay_chain_up[6], delay_ctrl[6]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(3)) dly_up7 (up_buf,delay_chain_up[7], delay_ctrl[7]);
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(6)) dly_up8 (up_buf,delay_chain_up[8], delay_ctrl[8]);

I tried the following based on what I found on a Cadence forum where k is a genvar-

generate
for(k=1;k<=`N_delays;k=k+1)
begin
delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma),.seed(24)) dly_up_array (up_buf,delay_chain_up[k], delay_ctrl[k]);
end
endgenerate

I am able to compile and run the unrolled instantiations, but I get the following compilation error for the looped instantiation-

Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "for<<--? (k=1;k<=`N_delays;k=k+1)"
"/home/scratch.amorakhia_libs/work/amorakhia+tsmc7+development+3/nvhs_tsmc7/am_tdc_delay/veriloga/veriloga.va",
line 58: syntax error.

I have tried the looping structure without the generate but that doesn't compile as well. I have attached the code with this post. Would really appreciate it if someone can tell me what I am doing wrong.

Thanks!

Title: Re: VerilogA-instantiation of array of modules using looping structure
Post by Andrew Beckett on Apr 29^th, 2019, 3:42am

Unfortunately I don't think this is supported in spectre currently. You can use for loops with a genvar within the analog block, but not in a module-level generate statement.

That does work with VerilogAMS using XCELIUM for example (although you'd have to change your two for loops to use different loop variables - for example k for the module-level loop and i for the loop within the analog block.

Regards,

Andrew.

Title: Re: VerilogA-instantiation of array of modules using looping structure
Post by Anish on May 2^nd, 2019, 10:09am

Thanks for your reply, Andrew.
I reached out to Cadence Support and they provided me with a work around using an instance array. I made the seed an input instead of a variable to support this new structure-

Code:

delay_cell #(.offset(50p),.step(tdc_step),.sigma(tdc_sigma)) dly_up_array[0:`N_delays-1] (up_buf,delay_chain_up, delay_ctrl, seed_up);

up_chop is a single electrical signal while delay_chain_up, delay_ctrl & seed_up are all arrays of electrical signals.

Anish