The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> Verilog AMS https://designers-guide.org/forum/YaBB.pl?num=1557553493 Message started by Vivek Saurabh on May 10th, 2019, 10:44pm

Title: Verilog AMS Post by Vivek Saurabh on May 10th, 2019, 10:44pm Hi. I have been trying to carry out mixed mode AMS simulation. For the schematic, I chose a verilog coded or gate, whose output is connected to veriloga coded xor gate and xor output goes to analog inverter (one using nmos and pmos). At two inputs of Verilog OR Gate I give two different vpulse with V0 as 0.85V and V1 as 0V and tr tf period as required. I am using connectlib ConnectRules18Vfullfast as interface. XOR gate and Inverters are working as expected but verilog coded OR gate is not showing any transition at output. It is always at level 0. When I replace OR with verilog Inverter in same schematic, it all works fine. What could be the reason, how do I get correct output from verilog OR? Is there something to do with connec rules? Image shows the case where 1st and 2nd waveform is input to OR and third waveform is output which doesnt show any transition.

Title: Re: Verilog AMS Post by Geoffrey_Coram on Aug 6th, 2019, 10:51am I'm having difficulty understanding your circuit from the text; perhaps a schematic would help. In particular, is your OR gate connected to both inputs of the XOR? In which case, the XOR would never be true, since its inputs are both high or both low. I also am not familiar with ConnectRules18Vfullfast. Is 0.85V high enough to trigger?

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