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Design >> Analog Design >> CML LATCH
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Message started by srinivasan0901 on Jun 25^th, 2019, 3:55am

Title: CML LATCH
Post by srinivasan0901 on Jun 25^th, 2019, 3:55am

I m trying to make a current mode logic latch at high speed around 8 GHz. The problem is that if i use separate bias at bottom, as shown in the figure, I dont get proper function, as the output voltage of one end remains at vdd/2 which should perhaps go down to zero. I dont know why is the problem. Is it due to wrong sizing of the cross coupled pair.

For the circuit shown, I chose bottom current source to be 30micro A, R =10k. so the total voltage swing during is vdd - VDD-(I*R) ie 900mv - 600mv. when clk bar becomes high, the cross coupled pair must make the circuit go to logic level 1 and 0 but here its moves to a common mode value of the output voltage ie to voltage around 750m , both the output level. Can anyone tell me exact reason for it

is there any tutorial on how to size CML circuits . I attach the image of the circuit which I Implement.

Title: Re: CML LATCH
Post by Horror Vacui on Jul 24^th, 2019, 2:08am

I think the following phrases are contradicting: "high speed", "30uA", "10kOhm".
For high speed one need "high" current and low resistance. 30uA seems very little even for a tiny transistor.

What do you mean by "he output voltage of one end remains at vdd/2 which should perhaps go down to zero"?
Why remain? If the input changes, than the output should change as well.
What are the logic levels you expects? CML never goes down to zero voltage. It is a differential logic, often as much as 100mV difference is enough for a reliable operation (more is welcome of course), and therefore even the logic "0" signal can be close to VDD in compared to static CMOS logic.

CML is current mode logic, the current is steered. Check the currents to debug it, not the voltage.