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Design >> Mixed-Signal Design >> LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation
https://designers-guide.org/forum/YaBB.pl?num=1563916147

Message started by repah on Jul 23^rd, 2019, 2:09pm

Title: LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation
Post by repah on Jul 23^rd, 2019, 2:09pm

Hello,

I would like to plot Iload vs. Vout for the Line Regulation for an LDO in Cadence Virtuoso and am wondering what the best approach would be.

I can put just an ideal current source, Idc using AnalogLib as the Load but that doesnt seem correct.

Should I use a controlled source in Cadence instead, like a current or voltage controlled source that links the two - if so - how would that be set up ?

Thank you.

Title: Re: LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation
Post by subtr on Aug 13^th, 2019, 11:53am

My approach is minimum number of simulations and maximum results. You should choose
DC simulation with ideal load current and get results for :
1. bias margins,
2. output voltage
3. reliability risks

AC Simulation for Stability, PSRR etc. should require your load current to be varied as LDO is non linear. The poles move with load current changes.

Your worst case regulation will be bad at worst case gain. So you will have to stabilize your LDO in order to even see the possible gain and regulation. Generally the stages go out of saturation to a low gain corner when stressed to max load, min supply, ss 125, min res corner. You would see that the bias margins are bad in this corner. This is because ss will enforce more overdrive requirement by previous stages and 125 will ensure the max vdsat.

In short you need to go around a small cycle of DC-AC to be really sure what your load regulation is. A first cut regulation can be achieved after biasing in DC simulation alone. And then sweeping load in the worst case I have mentioned above.

Step input regulation will require you to complete AC to see the dip due to current step and settling time. That's AC load regulation.