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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Short circuit with VDD3ALLP pad on C35B4C3 AMS technology
https://designers-guide.org/forum/YaBB.pl?num=1564494877

Message started by eddy19 on Jul 30^th, 2019, 6:54am

Title: Short circuit with VDD3ALLP pad on C35B4C3 AMS technology
Post by eddy19 on Jul 30^th, 2019, 6:54am

Hello,

I contact you because I’m using the pad called “vdd3allp” available in the C35B4C3 design kit from AMS, and when I run the LVS, I get the message below telling me that the labels vdd3r1! and vdd3r2! appear on two polarized lines both at the same potential, thus creating a short circuit.

Warning: #1 in VDD3ALLP
WARNING: Short circuit - Different names on one net:
Net Id: 1
(1) name "vdd3r1!" at location (1.45,322.9) on layer 604 "M3PIN"
(2) name "vdd3r1!" at location (99.45,322.9) on layer 604 "M3PIN"
(3) name "vdd3r2!" at location (1.45,267.1) on layer 604 "M3PIN"
(4) name "vdd3r2!" at location (99.35,267.1) on layer 604 "M3PIN"
The name "vdd3r1!" was assigned to the net.

I’ve tried to impose the values of vdd3r1! and vdd3r2! via the netset function on the schematics, but I didn’t manage to solve the problem. How can I do ?
Thank you in advance !
Eddy

Title: Re: Short circuit with VDD3ALLP pad on C35B4C3 AMS technology
Post by eddy19 on Sep 13^th, 2019, 8:00am

You need to use the METRES M2 layer by drawing on the layout a rectangle between the rails vdd3r1 and vdd3r2, and add a label vdd! at the bottom of the pad using the M2 PIN layer, as well as two other vdd3r labels! on the two rails vdd3r1 and vdd3r2 using the M4 PIN layer (the METRES layer M2 materializes a symbolic (non-physical) cut that allows the LVS to distinguish two polarized power rails at the same potential).

On the schematic side, you need to add a pin in/out vdd3r! and two resistors (called "short" and available in the PRIMLIB library), and polarize the two poles of the first to vdd3r! and the two poles of the second to vdd!.

E.Cartona