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Design >> Mixed-Signal Design >> LDO Simulation Output Results
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Message started by repah on Aug 20^th, 2019, 4:37pm

Title: LDO Simulation Output Results
Post by repah on Aug 20^th, 2019, 4:37pm

I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

I set the reference voltage to about 650mv and did a DC simulation.

The regulated voltage starts up and then dies as the VDD is ramped up.

What could be causing this ?

Thank you.

Title: Re: LDO Simulation Output Results
Post by Horror Vacui on Aug 30^th, 2019, 6:49am

Exchanged input terminals in an opamp could do that. The PMOS gate goes to supply and no current is flowing through the pass transistor. The load will discharge the output.