The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> VerilogAMS model for dual voltage clamper https://designers-guide.org/forum/YaBB.pl?num=1567514309 Message started by sanforyou on Sep 3rd, 2019, 5:38am |
Title: VerilogAMS model for dual voltage clamper Post by sanforyou on Sep 3rd, 2019, 5:38am Hi, I am writing a verilogAMS model for dual clamper. It's simple voltage clamp with upper threshold(upclamp) of 180mv and lower threshold(dnclamp) of 50mv. When upper threshold is reached then Output voltage is pulled down to ground and when lower threshold is reached then output voltage is pulled up to VDD. AMS model works fine on block level testbench but it starts chattering on top level and slows down the simulation drastically? Here is my verilogAMS code: Code:
Can anyone suggest improvement in the model to achieve this functionality without any slowdown? Thanks. |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |