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Design >> Mixed-Signal Design >> Integration Limits in Papers
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Message started by subtr on Dec 11^th, 2019, 11:31pm

Title: Integration Limits in Papers
Post by subtr on Dec 11^th, 2019, 11:31pm

I have seen that the limits of integrations are chosen by the groups who do PLL research. I find it okay to choose the lower cut off because our viewing time window is like a high pass filter not letting us see jitter of low frequency nature. But logically I find it impossible to choose a higher cut off for the integration limits unless there is some low pass filter(PLL) filtering out the phase noise by its bandwidth. Any high frequency phase movement of 5GHz will appear if we're viewing it long enough to account for say 10KHz(lower limit). Mathematically it's possible to take the PSD and filter it out in matlab. But is there any physical possibility of applying such an integration limit<fs/2 even possible without an LPF followed by it?

Title: Re: Integration Limits in Papers
Post by dnw on Jun 10^th, 2020, 4:10pm

Did you find something on this?
My understanding was there is inherent sampling when we talk about jitter.
For an inverter, there are two sampling events in each cycle. So when I look at particular edge jitter it has sampling fs so I should consider fs/2 as most of the high-frequency noise would already be folded.