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Design Languages >> Verilog-AMS >> Cannot see VCO phase noise
https://designers-guide.org/forum/YaBB.pl?num=1582573460

Message started by as_rf on Feb 24^th, 2020, 11:44am

Title: Cannot see VCO phase noise
Post by as_rf on Feb 24^th, 2020, 11:44am

Hi all,

I have a vco code with jitter and I want to observe phase noise
using PSS and PNOISE simulation. What I see is just a constant line for my phase noise.

Code:

`include "constants.vams"
`include "disciplines.vams"

(*ignore_hidden_state*)

module vco (vin, vout);
input vin;
output vout;
electrical vin, vout;
parameter real Vmin=0;
parameter real Vmax=Vmin+1.2 from (Vmin:inf);
parameter real Fmin=1.8e9 from (0:inf);
parameter real Fmax=3e9 from (Fmin:inf);
parameter real Vamp=1.2 from [0:inf);
parameter real ttol=1u/Fmax from (0:1/Fmax);
parameter real vtol=1e-9;
parameter integer min_pts_update=32 from [2:inf];
parameter real tran_time=10e-12 from (0:0.3/Fmax);
parameter real jitter_std_ui=0.002 from [0:1);
real freq, phase, jitter_rad, dphase, phase_ideal;
integer n, seed;
analog begin
@(initial_step) begin
seed = 671;
n = 0;
dphase=0;
jitter_rad=jitter_std_ui*2* `M_PI;
end
freq = ((V(vin)-Vmin)*(Fmax-Fmin)/(Vmax-Vmin)) + Fmin;
$bound_step(1/(min_pts_update*freq));
if (freq>Fmax) freq = Fmax;
if (freq<Fmin) freq = Fmin;
phase_ideal = 2* `M_PI*idtmod(freq, 0.0, 1.0, -0.5);
phase = phase_ideal + dphase;
@(cross(phase_ideal + `M_PI/2, +1, ttol, vtol) or cross(phase_ideal - `M_PI/2, +1, ttol, vtol)) begin
dphase = $rdist_normal(seed, 0, jitter_rad);
end
@(cross(phase + `M_PI/2, +1, ttol, vtol) or cross(phase - `M_PI/2, +1, ttol, vtol))
begin
n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
end
V(vout) <+ transition(n?Vamp:0,0,tran_time);
end
endmod

[img][/img]

Title: Re: Cannot see VCO phase noise
Post by Ken Kundert on Feb 24^th, 2020, 8:36pm

Pnoise is a small signal analysis. It only includes noise from small-signal sources, and you have none.

Furthermore, you should not use the jittery oscillator model with PSS as PSS requires periodic solution but the jittery oscillator does not have one.

-Ken

Title: Re: Cannot see VCO phase noise
Post by as_rf on Feb 25^th, 2020, 10:37am

Thank you very much for clarification.

So is there anyway that I make a behavioral VCO and check its phase noise in Cadence virtuoso ? or make a behavioral fixed-frequency oscillator ? Does not have to be VCO.

Title: Re: Cannot see VCO phase noise
Post by as_rf on Feb 25^th, 2020, 11:43am

My Goal is to be able to make behavioral PLL (Or circuit) and check its phase noise.
But I am very confused. There is no solid tutorial for this.

Title: Re: Cannot see VCO phase noise
Post by Ken Kundert on Feb 25^th, 2020, 9:31pm

Turn off the jitter and add noise using the small signal noise functions.

-Ken

Title: Re: Cannot see VCO phase noise
Post by as_rf on Feb 26^th, 2020, 12:11am

I dont know how to do that. :(

Title: Re: Cannot see VCO phase noise
Post by Ken Kundert on Feb 27^th, 2020, 12:31am

Set the jitter parameters to zero, so your system will have a periodic steady state response. And then add functions like flicker_noise and white_noise to the models to inject the small signal noise. These functions were demonstrated in the phase domain models given earlier in the paper.

-Ken

Title: Re: Cannot see VCO phase noise
Post by Andrew Beckett on Feb 29^th, 2020, 4:33am

In addition (once the jitter code has been removed or made inactive to ensure it's periodic) there genuinely is a hidden state in there (you are turning off the hidden state checks). The variable n is only being set within the @cross. You can avoid that simply by writing:

Code:

@(cross(phase + `M_PI/2, +1, ttol, vtol) or cross(phase - `M_PI/2, +1, ttol, vtol));
n = (phase >= -`M_PI/2) && (phase < `M_PI/2);

There's no begin and end - simply put a semi-colon after the @(cross) as this then ensure's there's a timestep at (or close) to the transition. The variable n is then assigned on every step. If I do this, the code runs in PSS without needing the hidden state being ignored (note I removed that too from the code):

Code:

`include "constants.vams"
`include "disciplines.vams"

module vco (vin, vout);
input vin;
output vout;
electrical vin, vout;
parameter real Vmin=0;
parameter real Vmax=Vmin+1.2 from (Vmin:inf);
parameter real Fmin=1.8e9 from (0:inf);
parameter real Fmax=3e9 from (Fmin:inf);
parameter real Vamp=1.2 from [0:inf);
parameter real ttol=1u/Fmax from (0:1/Fmax);
parameter real vtol=1e-9;
parameter integer min_pts_update=32 from [2:inf];
parameter real tran_time=10e-12 from (0:0.3/Fmax);
parameter real jitter_std_ui=0.002 from [0:1);
real freq, phase, jitter_rad, dphase, phase_ideal;
integer n, seed;
analog begin
@(initial_step) begin
// seed = 671;
n = 0;
// dphase=0;
// jitter_rad=jitter_std_ui*2* `M_PI;
end
freq = ((V(vin)-Vmin)*(Fmax-Fmin)/(Vmax-Vmin)) + Fmin;
$bound_step(1/(min_pts_update*freq));
if (freq>Fmax) freq = Fmax;
if (freq<Fmin) freq = Fmin;
phase_ideal = 2* `M_PI*idtmod(freq, 0.0, 1.0, -0.5);
phase=phase_ideal;
/*
phase = phase_ideal + dphase;
@(cross(phase_ideal + `M_PI/2, +1, ttol, vtol) or cross(phase_ideal - `M_PI/2, +1, ttol, vtol)) begin
dphase = $rdist_normal(seed, 0, jitter_rad);
end
*/
@(cross(phase + `M_PI/2, +1, ttol, vtol) or cross(phase - `M_PI/2, +1, ttol, vtol));
// begin
n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
// end
V(vout) <+ transition(n?Vamp:0,0,tran_time);
end
endmodule

Andrew

Title: Re: Cannot see VCO phase noise
Post by as_rf on Feb 29^th, 2020, 10:02pm

Thank you very much. But I think still I cannot observe phase noise as explained before.

I wanted to do some voltage domain behavioral modeling for PLL phase noise. But it seems that it is very hard. You spend a lot of time on behavioral model then you regret. It is much easier to make the circuit and do the rest.

In the next step, I want to learn how to plot phase noise of a PLL (schematic design). Still there is no solid tutorial for it. :-[

Title: Re: Cannot see VCO phase noise
Post by Andrew Beckett on Mar 1^st, 2020, 12:32am

Why is it very hard to do the modelling of the noise? Ken already suggested how to do that - it's just a matter of using the flicker_noise and white_noise functions in your Verilog-A models. There are countless models out there that do this, and probably some in these forums too.

Andrew.